With the rapid development of artificial intelligence (AI) and high-performance computing (HPC) applications, the traffic of existing data centers is growing, which puts forward higher requirements for data bandwidth and data transmission rate, and the problems of power consumption and cost are becoming increasingly serious. To meet these challenges, a variety of methods are proposed, including reducing the characteristic size of transistors, exploring new transistor structures such as FinFET and GAAFET, using quantum information technology, etc.1^–3 With the transistor size approaching the physical limit, advanced packaging technology has become an effective solution, and 3D chiplets, heterogeneous integration, and co-packaged optics (CPO) have developed rapidly.2 As shown in Fig. 1, the development of CPO has evolved from traditional copper interconnection to pluggable optical modules, then to on-board optics (OBO) in the transitional stage, and then to CPO. The optical transceiver module is getting closer and closer to the switch application specific integrated circuit (ASIC). The reason for this development trend is that the traditional copper interconnection has huge losses at high transmission rates. It is difficult to transmit data beyond a few centimeters. The fan-out density of traditional pluggable optical modules can no longer meet the growing bandwidth requirements, and the power consumption is too high. Using CPO packaging brings the following advantages: (1) Reduce power consumption, place electro-optical components closer, and reduce energy loss and power requirements. Johnson et al.5 observed that using CPO in a 1.6 T switch can save more than 50% of power consumption compared with using pluggable optical modules,5 as shown in Fig. 2. (2) Support higher bandwidth and data rate. (3) It improves interconnection performance and signal integrity, and reduces delay and insertion loss.

The current 2.5D/3D CPO has common challenges in electrical, thermal, and mechanical aspects. Therefore, there is an urgent need for new materials and processes to achieve the following goals: to achieve high-speed, high-density, low loss, reliable electrical interconnection; solve the thermal management problem of high-power electronic integrated circuit (EIC) and temperature-sensitive photonic integrated circuit (PIC) on the same substrate; reduce substrate warpage; and ensure that the bumps/solder posts between the chip and the packaging substrate and the ball grid array between the packaging substrate and the motherboard have a high degree of electrical reliability.6 Glass has a good combination of characteristics, which can solve the common challenges faced by CPO.7 Glass can be processed by wafer-level process or panel-level process, which can realize large-size and low-cost glass substrate. It has a low dielectric constant and dielectric loss, which can reduce the delay and loss in signal transmission. With excellent surface smoothness, it can meet the requirements of fine-line and narrow spacing processes, and realize the manufacturing of high-density interconnection structure. It is insensitive to temperature and humidity fluctuations and exhibits good stability under high-temperature and high-humidity conditions.8 Its coefficient of thermal expansion (CTE) can be adjusted by changing the composition, to choose between the low CTE of the silicon chip and the high CTE of the PCB board, to achieve good CTE matching and reduce warpage.8 In addition, the glass has a wide range of spectral transparency and low optical loss, which can be used to make optical waveguides. The good electrical and optical properties of glass enable the fabrication of the electrical interconnection structure and optical interconnection structure on the same substrate. In 2021, Corning proposed a concept of glass-based optoelectronic packaging integrating glass optical waveguides, a passive aligned glass waveguide connector, and an electrical interconnection structure. The structure is shown in Fig. 3(a). The process feasibility of the optical interconnection structure and the electrical interconnection structure is verified, and the two structures are made of the same glass. The optical interconnection structures include low-loss ion-exchange waveguides, mechanically passively aligned optical fiber connectors, and other structures. The propagation losses of the two kinds of waveguides with different refractive indices tested at 1310 nm are 0.08 and 0.11dB/cm, and the coupling losses of the waveguides and single-mode fibers are 0.3 and 0.6 dB at 1310 nm. The electrical interconnection structures include through-glass-via (TGV) and cavity, which are important for the mounting of PIC and the evanescent coupling between PIC and optical waveguides. This structure provides a new option for CPO.7

At present, there are two main technical paths for CPO-oriented glass substrate technology. One is the optoelectronic hybrid integrated glass substrate scheme represented by Corning, as shown in Fig. 3(a). Another architecture is shown in Fig. 3(b). The core layer of the glass substrate is glass, and the core layer runs through the TGV structure for vertical interconnection. The L/S (line width/line spacing) above and below the core layer is thinner than the traditional substrate, and the line density is higher. The chip is connected to the substrate by flip chip (FC) through copper pillar or solder balls.9 In this scheme, glass is only used as the intermediary layer of high-performance electrical interconnection, does not include the waveguides structure based on the glass itself, and light is coupled into and out of the PIC via edge coupling.10

This review takes the glass substrate for CPO as the theme, and conducts a systematic survey of its technical system and state-of-the-art. First, the classification of glass, the making and filling of the TGV, and the making of the redistribution layer (RDL) are introduced. The high-speed performance of the electrical interconnect structures is also detailed. Then, the current state of optical interconnects for CPO and the fabrication techniques for optical waveguides on glass substrates are reviewed. Finally, the existing application results are briefly summarized, and the prospects are given.

Glass is an amorphous material composed of several oxides. According to Zachariasen, these oxides can be divided into the following categories: network formers, such as SiO2, GeO2, or P2O5, can form glass by themselves; intermediates, such as Al2O3 and TiO2, are difficult to form glass alone, but they can combine with network formers; finally, network modifiers, such as Na2O, K2O, CaO, or BaO, can be embedded in the matrix composed of glass formers, but their molecular bonding structures do not match, so their bonding with the matrix is weak.8^,11 Among them, network formers are the skeleton of molecular networks. The intermediate can form a strong bond with the skeleton, and the bond strength is between the strong covalent bond of the skeleton itself and the weak covalent bond of the network modifier. Because of the weak bond between the network modifier and the skeleton, alkali metal ions such as sodium ions and potassium ions can be replaced by other ions without damaging the original skeleton structure. This is the basis for the formation of optical waveguides on glass substrates through ion exchange (IOX) technology, which will be introduced in detail in the fourth chapter of this article. The physical and chemical properties of glass vary with its composition. There are four common types of glass in the field of microprocessing: borosilicate, soda lime, quartz, and alkali-free. The performance comparison between various glasses is shown in Table 1 below.

Among them, alkali-free glass is used in the field of electronic packaging due to its low mobile ion concentration, desirable insulation performance, and high frequency characteristics.12^,13 This is distinctly reflected in the research of Tanaka et al. The alkali-free glass (EN-A1) used by them has an insertion loss of 0.48 dB at 30 GHz, realizing excellent high-frequency signal transmission.14 However, to realize optoelectronic integration on the same glass substrate, there is a key contradiction: when making optical waveguides based on IOX technology, there need to be mobile alkali metal ions in the glass network, which means that alkali-free glass with excellent performance in electrical packaging cannot be used in optical packaging based on IOX technology. By contrast, the 3D optoelectronic hybrid glass interlayer made by Chou et al. uses a photosensitive polymer (benzocyclobutene) as an optical waveguide, as shown in Fig. 4.15 This technical path does not rely on the ion exchange on the glass to avoid this contradiction, but the polymer waveguide has a large loss in common communication bands, with a propagation loss of 0.4 to 0.8dB/cm at 1310 nm. If alkali glass is used as the packaging substrate, although it can support the preparation of IOX waveguides, it will introduce the reliability problem caused by electron migration. Another study added a Si3N4 barrier layer between the alkali glass substrate and the metallized copper layer, which effectively solved the problem of copper migration, making the alkali glass not only capable of preparing IOX optical waveguides but also with competent electrical packaging reliability.7^,16 In summary, alkali-free glass, owing to its low dielectric constant, low dielectric loss, and excellent insulation properties, has been widely adopted in the field of electronic packaging. Optical applications such as lenses and waveguides, however, place greater emphasis on optical characteristics rather than strict requirements for dielectric loss. Moreover, technologies such as IOX optical waveguides are typically implemented in alkali-containing glass. In future CPO applications, glass materials will need to serve dual roles—as both optical waveguides and high-speed electrical interconnects. Therefore, through compositional tuning (such as adjusting the content of alkali ions) and process optimization, glass may maintain low dielectric loss while also meeting the fabrication requirements for optical waveguides, thereby enhancing its suitability for CPO integration.

Although glass wafers (usually 200 to 300 mm wafer) and glass panels (500mm×500mm or larger rectangular panels) both use glass as the substrate, glass panels mainly focus on large areas, low costs, high line width, and line spacing, making them suitable for large-scale packaging. Glass wafers have a higher cost and lower line width and spacing and are used in radio frequency (RF), AI applications, and other scenarios. Similarly, there are significant differences in the RDL stack structure using different processes. These differences are due to factors such as size, processing methods, and selection of dielectric materials.17

On glass substrates, the interconnect density between RDL and TGV is a key indicator in advanced packaging. RDL supports line density >500lines/mm with a line width of 2μm. The typical commercial diameter of TGV is 40μm, and the interconnect density is ∼100 to 2500vias/mm2 at a pitch of 20 to 130μm. Overall interconnect I/O density >10,000I/Os/cm2, better than organic 1000I/Os/cm2.

First, the impact of size differences on RDL stack architecture. The glass wafer adopts a 200/300-mm sized wafer with very low surface roughness (Ra<1nm). Manufacturing of stacked structure: Similar to silicon wafer technology, thin dielectric layers (<5 to 10μm) can be used, with line width and spacing up to 2μm or less, and RDL can reach 3 to 5 layers or even higher. The size of glass panels is 500mm×500mm or larger, with a higher surface roughness compared with glass wafers and a dielectric layer thickness of 10-30μm. RDL line width and spacing are generally above 5μm, with 1 to 3 layers of RDL. Substrate structures employing glass as the core layer in combination with Ajinomoto build-up film (ABF) technology have demonstrated total routing layer counts of ∼16 to 24 layers under production-relevant conditions, with some technology demonstrators exceeding 30 layers. In this integration scheme, the glass primarily serves as a mechanically stable and highly planar core, as well as a platform for vertical interconnects such as TGVs, whereas the high-layer count routing is realized within the mature organic build-up layers. This approach effectively avoids the brittle fracture and severe warpage issues that would arise from directly stacking multiple thin-film RDLs on glass surfaces. The reason for limiting the number of stackups in these two processes is that the thermal expansion coefficients of glass materials and organic materials do not match.

Second is the difference in dielectric materials, which is also one of the most critical differences. The dielectric materials used in glass wafer RDL are mainly thin film polymers of semiconductor processes, such as PI, PBO, and SiO2/SiN (thin films). These dielectric materials have a relatively thin thickness, ranging from 1 to 5μm, and a low loss tangent. It is possible to manufacture fine RDLs at the 2μm level, whereas glass panel RDL dielectric materials use large-area sprayable packaging-grade polymers such as ABF, which can have a thickness of 10 to 30μm and high losses, with tanδ typically >0.01.

Finally, the way of metallization is different, which means the RDL manufacturing process is different. Glass wafer RDL can be manufactured with extremely fine line width and spacing using the Damascus process, whereas glass panels usually use a semi-additive method with larger line width and spacing, which will be discussed in detail in later chapters.

The typical manufacturing process of a glass substrate is shown in Fig. 5 below: the first step is to make and fill the TGV. The filling step involves electroplating of the adhesive layer and the seed layer. After electroplating, the vias are filled. The second step is chemical mechanical polishing (CMP), which can make the surface smooth and prepare for subsequent graphing. The third step is to fabricate the circuit pattern on the flattened metal layer with photolithography technology, and then etch the redundant metal layer to form a layer of horizontal wiring. The fourth step is to deposit a layer of dielectric material on the patterned surface. In the wafer-level process, polyimide (PI) is often spin-coated as the dielectric layer, and in the panel-level process, ABF is used as the build-up material. Then, vias are drilled on the dielectric layer to expose the metal pad. The fifth step is copper plating in and on the surface of the dielectric via. Repeat steps 3 to 5 above to complete the construction of multilayer RDL and finally form the laminated structure of the glass substrate. After all layers are fabricated, the glass is diced into individual units. The overall electrical performance of the glass substrate depends on the performance of TGV and RDL. The processes involved in these two structures and their high-speed electrical performance will be described in detail below.

TGV technology refers to the key technology of 3D interconnection based on through or blind vias in forming, seed layer sputtering, electroplating, and filling.18 Signal integrity, thermal conductivity, and power density are the key parameters to measure the performance of TGV. These key parameters depend on the size, shapes and filling process of TGV.17 The manufacturing of TGV with a high aspect ratio and the filling of copper in the via are the key challenges in the manufacturing of glass substrate.17 At the same time, the fabrication of TGV with high interconnection density and high quality is crucial to the improvement of bandwidth.19

Although glass has excellent properties, it is a hard and brittle material. Long processing time, high processing cost, and poor surface quality make it more difficult to manufacture TGV. The development of process capability has significantly improved the manufacturing capacity of TGV.8 At present, the methods for making TGV include wet etching, abrasive jet machining (AJM), laser ablation, electrochemical discharge machining (ECDM), laser-induced deep etching (LIDE), etc.18Figure 6 is a schematic diagram of various glass processing methods. Wet etching with hydrofluoric acid (HF), sodium hydroxide (NaOH), and other reagents is the most commonly used method in the processing of glass microstructure. It uses metal, silicon, etc. as a mask and then dissolves the glass with chemical reagents to etch the required structure. Wet etching has the advantages of simple operation, controllable structure, high material removal rate, and low cost compared with dry etching, but it uses HF, which is a dangerous chemical. In the process of etching, there is lateral drilling and etching, which requires a customized mask, and it is difficult to produce small-sized, high-aspect-ratio through vias.8^,18 AJM is a mechanical etching method, which realizes material removal by a high-speed jet of micron-sized solid particles (such as aluminum oxide) impacting the object surface, and also requires a mask.20 Compared with the above wet etching, AJM has a higher material removal rate and does not require the use of hazardous chemical reagents, but its machined surface roughness is high. The selectivity between the mask and the substrate is poor. Moreover, edge collapse will occur at the TGV edge, as shown in Fig. 7. It is suitable for making large-sized through-glass vias, and there are restrictions on through-vias with small spacing and high aspect ratio.8^,18 Laser ablation is a method based on heat. It uses long pulse lasers, short-wavelength lasers (such as ultraviolet), ultrashort pulse lasers, etc., based on carbon dioxide (CO2). The laser generated by the laser acts on the substrate material to vaporize, melt, and splash, and then removes the target structure. Compared with the traditional etching method, the laser ablation has higher etching efficiency and lower surface roughness, but the material removal process depends on the thermal reaction of the material itself. The stress generated by the thermal reaction has a wide range of distribution, and it is easy to go deep into the areas not irradiated by the laser during the cooling process, causing cracks and recondensed particles8 in these areas. The through vias made by the UV laser are shown in Fig. 8. It is suitable for making through vias with high aspect ratio and high density, but the impact of thermal effect is a major challenge in the manufacturing process. ECDM is a hybrid non-traditional micro machining process, which combines the principles of electrochemical machining (ECM) and electrical discharge machining (EDM). The basic process is as follows: the tool electrode (cathode) and auxiliary electrode (anode) are immersed in the electrolyte. After the voltage is applied, a hydrogen film will be formed on the surface of the tool electrode, and spark discharge will be generated, and the workpiece material23 will be removed through the joint action of hot melt and chemical etching. ECDM offers high processing efficiency. However, the via formation process relies on electrode needles, and fabricating needle tips finer than 150μm is challenging. As a result, the vias currently produced are mostly above 200μm in diameter.18 LIDE is also a hybrid process. First, the processing area is irradiated by a laser to modify it, and then the modified area is wet etched. The TGV depth-width ratio processed by LIDE can reach 10:1 or even higher, and even 50:1 under some conditions, with high processing quality and speed. In conclusion, laser ablation and LIDE are suitable for processing TGV with high density and high aspect ratio.24Table 2 summarizes various glass processing technologies.

When fabricating TGVs using LIDE, the cross-sectional profile and sidewall roughness of TGVs are collectively influenced by laser parameters (such as power and focal length) and the subsequent etching process. Based on their geometric profile, TGVs can be classified into cylindrical, conical, and hyperbolic types, as shown in Fig. 9(a). The degree of inclination for conical and hyperbolic TGVs can be characterized by the taper angle, as illustrated in Fig. 9(b); when the taper angle is 0°, both types revert to a cylindrical shape. The shape of TGVs influences the thermal, mechanical, and electrical properties of glass substrates. In the following discussion, the focus will be placed on their impact on high-speed electrical performance. Fang et al. developed TGV simulation models for double-layer vertical interconnect structures with varying tapers and sidewall roughness to investigate their correlation with high-frequency performance. The simulation results showed good agreement with experimental measurements up to 40 GHz, with the insertion loss and delay results presented in the corresponding Fig. 10.25 The findings indicate that, at the same frequency and roughness level, cylindrical TGVs exhibit the lowest insertion loss and signal delay. Furthermore, under identical conditions of frequency, roughness, and taper, conical TGVs outperform hyperbolic ones in terms of loss and delay. For all three profiles, insertion loss and delay increase proportionally with taper, roughness, and frequency. This behavior is attributed to the rise in parasitic resistance, internal inductance, and conductance as these parameters increase, which degrades impedance matching and elevates insertion loss. The delay is positively correlated with both capacitance and inductance (τ∼(LC)1^/2). Although an increase in taper reduces parasitic capacitance, the increase in parasitic inductance is more significant, resulting in an overall rise in delay. Notably, the inductance of hyperbolic TGVs is more sensitive to changes in taper and roughness, which is why they exhibit the greatest delay under identical taper, roughness, and frequency conditions. Therefore, in practical manufacturing, optimizing the process to achieve low-roughness, cylindrical vias is crucial. Such vias can suppress parasitic effects, thereby offering superior signal integrity—such as lower insertion loss and reduced delay—in high-speed interconnects. Regarding this research, we have an extended consideration: the shape of the via affects the difficulty of the subsequent filling process, potentially causing issues such as discontinuous filling, which in turn impacts the high-speed performance of the via. In the study by Fang et al., it was mentioned that cylindrical vias with low roughness exhibit the best high-frequency electrical performance. However, the filling of cylindrical vias poses a challenging issue. This section subsequently introduces the research by Yang et al. on filling cylindrical vias.

The filling of high-quality TGV metalized vias faces two major challenges: adhesion between metal and glass and integrity of the filling. Due to the low surface energy of glass, its bonding strength with metal is poor, which can easily lead to discontinuity of the barrier layer and seed layer, and delamination occurs in subsequent processes.26 In addition, if there are seams and voids in TGV, these defects can damage the electrical performance of the vias, and TGV may cause circuit failure due to an open circuit.26 Optimizing the process flow, changing the electroplating additive system, and altering process parameters can effectively solve this challenge.17^,26^,27 The filling methods for TGV mainly include bottom-up filling, butterfly model (BFT) filling, and conformal filling.26 Bottom-up filling refers to adding inhibitors and accelerators at the top and bottom of the via, respectively, so that the filling rate at the bottom of the via is greater than that at the top, achieving bottom-up filling and avoiding the occurrence of seams and voids.26 BFT utilizes a single inhibitor to achieve the deposition of copper from the center to the top through the concentration gradient established within the through-via. The filling process begins at the sidewall of the through-via center, with a cross-section resembling a butterfly, hence the name butterfly-shaped filling. After the butterfly shape is formed, the filling changes to a bottom-up filling from the center to both sides.28 The copper deposition rate on the sidewall, inside, and surface of the via filled with conformal filling is the same. Due to the same filling rate, defects are prone to occur when filling into the middle of the via.26

Yang et al. used LIDE technology to manufacture glass vias and deposited adhesive and seed layers using double-sided physical vapor deposition (PVD). They also deposited seed reinforcement layers using electroless copper plating and achieved complete copper filling from bottom to top. Through experiments, the optimal time for depositing a seed reinforcement layer by electroless copper plating was obtained, and the correlation between through-via diameter and filling characteristics was explored. Through the synergy of process and structural parameters, a straight TGV through-via with a diameter of 15μm and a depth of 300μm (aspect ratio of 1:20) was successfully prepared, as shown in Fig. 11(a).19 Kudo et al. proposed a new TGV filling method in which a bridge-shaped copper structure is rapidly deposited along the top of the via after uniform copper plating on the surface and sidewalls of the via. This filling method avoids common via center void defects caused by conformal filling, and saves time compared with bottom-up filling. The results indicate that up to 10 million copper bridges embedded in the glass substrate did not experience filling failure, demonstrating good process reliability, as shown in Fig. 11(b).27 When choosing the actual filling method, it should be based on the morphology and via size of TGV to achieve the best filling effect.

RDL is a metal wiring layer (mainly copper) made on the surface of a chip/intermediate layer through processes such as photolithography, electroplating, and etching. RDL redistributes the native I/O pads of the chip from their original positions. This technology breaks the position and density limitations of chip I/O through micrometer-level precision wiring, enabling electrical interconnection across regions and materials. At the same time, it can be well compatible with chips of different sizes and quantities, further increasing the number and integration scale of chips packaged in a single batch.

In the glass substrate CPO, RDL collaborates with TGV, mentioned earlier, to construct a three-dimensional network of “horizontal wiring + vertical conduction”, breaking through the density bottleneck of planar interconnection and achieving three-dimensional interconnection between different chips in CPO.

There are two technical routes for RDL manufacturing of glass substrates, namely, panel-level processes and wafer-level processes. The wafer-level process can be well matched with silicon production lines and can use the Damascus process. This can process the RDL line width and spacing of wafer-level processes to below 5μm. Therefore, the adoption of wafer-level processes mainly focuses on the demand for low line width and spacing. The panel-level processes are as follows. First, glass panels can be larger than glass wafers in terms of size limit. The commonly used glass wafer size is up to 12 inches with a diameter of around 300 mm. FOPLP developers use various panel sizes, including Licheng Technology and Silicon Products, which use 515mm×510mm panels. Sunlight and Moonlight use glass panels in two sizes: 300mm×300mm and 600mm×600mm. Due to the rectangular shape of the panel, the utilization rate of the carrier is significantly better than that of wafer-level processes. However, due to the large size of the glass panel, it is difficult to ensure the flatness of the plane, and the degree of thermal warping at the edges is greater. CMP technology cannot be used, and most methods use semi-additive process/modified semi-additive process (SAP/mSAP), with line width and spacing usually above 5μm.

There are significant differences in the methods of manufacturing RDL between panel-level and wafer-level processes. This section discusses the manufacturing technology of RDL on glass substrates using panel-level and wafer-level processes.

The manufacturing of RDL on traditional panel-level glass substrates is mainly represented by Corning, Qualcomm, and Atotech companies, following the SAP/mSAP method selected for the processing path of organic substrates. The following is the process flowchart of SAP technology: first, seed layer deposition is completed by chemical plating or ion sputtering, followed by coating, photolithography, electroplating of the metal layer, removal of excess seed layer and photoresist, and then multiple SAPs are carried out to achieve the manufacturing of multilayer RDL. The line width and spacing of RDL using this process are usually ≥5μm.29

The main challenge in manufacturing low line width and line spacing RDL using traditional SAPs is the removal of excess seed layers. For the seed layer on the deposited insulation layer, the thickness produced using traditional sputtering technology is approximately between 100 and 200 nm, whereas the seed layer produced using chemical deposition is ∼500nm. If the line width and spacing of RDL are less than 5μm, the thickness of the removed seed layer exceeds 10% of the line width, which will cause angular deviation of Cu lines due to root cutting. In addition, it also includes the problem of leakage caused by seed residues in ultra-small gaps, as shown in Fig. 12.

Liu et al. have developed RDL copper trace transfer (CTT) and photolithography trench embedding (PTE) methods.30 As shown in Fig. 13(b), in the CTT method, fine copper circuits are prefabricated on thin copper foil using photolithography and electroplating methods and then transferred to the polymer film layer previously bonded to the substrate by pressing. Then peel off the carrier and etch the sharp copper foil. The photolithography groove embedding (PTE) study used TMMF-2014 dry film and PN-0371D provided by Tokyo Ohka Kogyo Co., Ltd. The production process involves coating a photosensitive dielectric material, PN-0371D, onto a TMMF-2014 dry film on a glass substrate, followed by photolithography and PVD deposition of thin titanium and copper as barrier and seed layers. The sedimentation thickness is titanium and copper. After filling the groove, remove the copper on the surface of the dry film by chemical corrosion. This method can be used to manufacture line widths and spacing of 1.5 to 5μm. The process is shown in Fig. 13(a).

For the process selection of glass wafer-level RDL, it can be compared with silicon wafer RDL, which is usually determined based on the target line width and spacing. If the target line width and spacing are below 5μm, the Damascus process is generally used; if the target line width and spacing are above 5μm, SAP technology similar to panel level is used.31 The following text introduces two methods for manufacturing RDL at the glass wafer level process.

First, as shown in Fig. 14(a), the polymer is used to start manufacturing on the glass wafer that has completed TGV. First, spin-coat polymers such as PI or BCB on the wafer and form a 4 to 7 mm thick intermediate layer. Then apply photoresist and mask, and use photolithography techniques (alignment and exposure) to create holes on PI or BCB. Afterwards, titanium and copper are sputtered onto the entire wafer. Use photoresist and mask, and then use photolithography technology to open and redistribute trace positions. Remove the photoresist after opening the photoresist. Then complete the etching of titanium/copper and RDL. This method has been used by OSAT to manufacture RDL for wafer-level chip-scale packaging,32 embedded wafer-level (fan-out) ball grid array packaging,33 and (fan-out) redistribution chip packaging34 (without using semiconductor devices).

The second method is the copper Damascus method, which is mainly an improved copper metal RDL made from traditional semiconductor back-end lines, as shown in Fig. 14(b). For the copper Damascus process, start manufacturing on the glass wafer that has completed TGV, as shown in detail in Fig. 14(b). First, the dielectric layer is prepared by the PECVD method, mainly using PI. A mask template is used, and then alignment and exposure are performed using photolithography technology, followed by opening holes, sputtering titanium and copper on the entire chip, and electroplating copper. CMP is then performed on the copper and titanium/copper. The above steps are repeated to manufacture multilayer RDL. Generally speaking, the copper Damascus method can achieve thinner structures (dielectric layer and copper RDL), finer spacing, and smaller line width and spacing, which will be the focus of manufacturing RDL on glass wafers.

Compared with traditional organic substrates such as BT or ABF and silicon via (TSV), glass substrates have a low dielectric constant Dk, low loss angle, low surface roughness, and good thermal stability. These characteristics result in TGV and RDL exhibiting extremely low insertion loss and high signal integrity.

The high-frequency performance of TGV is influenced by various parameters, including via geometry, metallization method, Dk/Df of glass, etc. Töpper et al. studied the influence of TGV geometry on signal transmission.35 The geometric parameters studied include the diameter and shape of the through-hole (conical or cylindrical), and are analyzed using three-dimensional full-wave electromagnetic simulation methods. Figure 15 shows the 3D model of the through-hole structure used in the simulation, and depicts the three important geometric parameters of TGV in the upper left corner.

First, the influence of through-hole diameter d was studied, with diameters set to 50, 100, and 200μm, h=500μm, and α=90°, respectively. The results shown in Fig. 16 indicate that this variation in through-hole diameter has no significant effect on the transmission of the through-hole. Beyond 10 GHz, the transmission of 200μm through holes is severely reduced, with only about 60% power transmission at 50 GHz. The transmission of 50 and 100μm through holes remains above 85% across the entire bandwidth.

Then simulate the through-hole angle. The through-hole diameter and substrate thickness are d=50μm and h=500μm, respectively. Below 20 GHz, the impact on transmission is minimal. Above this frequency, the transmission decreases as the angle decreases. When α=60deg, only 23% of the power is transmitted at 40 GHz. Therefore, through holes have better performance than tapered through holes.

Ge et al. fabricated a TGV structure on an 8-inch glass wafer that supports 110 GHz high-frequency signal transmission.36 They simulated the transmission performance of a ground signal ground (GSG) transmission line composed of TGV and RDL. RDL adopts a coplanar waveguide (CPW) structure. Figure 17 shows the corresponding 3D model in HFSS.

Based on the actual manufacturing capability and experimental testing conditions of TGV, Ge et al. simulated the diameter, RDL line width, spacing, and thickness of TGV. The S₂₁ results simulated in the range of 1 to 110 GHz are shown in Fig. 18.

In Fig. 18(a), T and B represent the top and bottom opening diameters of TGV, respectively. When the diameter of TGV is changed, the overall trend of the S parameter remains unchanged, indicating that the influence of the top and bottom opening diameters of TGV on transmission loss is relatively small. The range of −3dB bandwidth is from 85 to 92 GHz.

Figure 18(c) shows that compared with the spacing, the pitch of 125 and 150μm produces similar and smaller transmission losses compared to the pitch of 100μm.

The surface ripples in Figs. 18(a), 18(c), and 18(d) with the changes in the relevant parameters are not very obvious, whereas for the line width in Fig. 18(b), the resolution is high. The reason for the appearance of surface ripples is not explained in Ge et al.’s text, and we think that it may be due to a mismatch between the hole’s impedance and the wire.

Kim et al. compared the insertion loss of the glass substrate TGV and silicon substrate TSV, as shown in Fig. 19, and it can be seen that the high-frequency insertion loss of glass substrate TGV is lower.37 The TGV diameter is 60μm, and the TSV diameter is 32μm.

In the glass core substrate, RDL undertakes the high-frequency signal transmission from chip to TGV and TGV to TGV, which is another core link that determines the high-frequency performance of the entire package. Compared with traditional organic substrates (ABF, BT) and silicon interlayer RDL, glass substrate RDL has three natural advantages: ultra-low surface roughness, extremely low dielectric loss (Df<0.005 @ 40 GHz), and the ability to achieve ultra-fine wire spacing below 2μm. The glass substrate carries the role of through-hole interconnect in the transmission path, and its low-loss characteristics improve the overall high-frequency characteristics. At the same time, RDL, which is adjacent to glass, is affected by the low-loss characteristics of glass, resulting in superior high-frequency characteristics. Assuming that the high-speed interconnection path is only RDL and the dielectric materials in the field distribution region between the RDL signal and the reference plane are ABF or PI materials on glass, then this part can be said to be the same as the electrical properties of organic substrates and silicon substrates.

According to the simulation study of Ge et al. in 110 GHz high-frequency signal transmission mentioned above, the S21 simulation results of GSG transmission line models with different linewidths are shown in Fig. 18(b). The transmission loss increases with the increase in transmission line width. However, it should be considered that a too thin line width can lead to higher manufacturing difficulty. According to Fig. 18(d), the thickness of the RDL has little effect on transmission loss. However, a thicker RDL will result in greater warping.

Table 3 compares the RDL of glass substrate, silicon substrate, and organic substrate.

Thanks to the combination of glass ultra flat surface and low-loss polymer medium, glass substrate RDL can have extremely low high-frequency transmission loss. In the frequency band above 110 GHz, its performance surpasses that of traditional organic substrate RDL, whereas its manufacturing cost is lower than that of silicon substrate,38 and it has the potential for large panels and low-cost mass production.

Glass substrates, with their scalability (supporting large-scale and panel-level processing), excellent thermal stability, high interconnect density, and broad optical transparency, present a highly promising solution for advanced integration systems such as CPO. Research conducted by Lee et al. on large-sized glass substrates further validates their feasibility in practical applications.39 The study utilized a two-layer glass substrate with a core thickness of 500μm and dimensions of 100mm×100mm. The ABF dielectric layers were laminated on both sides of the glass core via a semi-additive process (SAP). The chip was attached to the substrate surface using epoxy adhesive, whereas the interconnection between the substrate and the PCB was achieved through a BGA solder ball array. The research focused on evaluating the reliability of the secondary interconnects (BGA solder joints from the glass substrate to the PCB) under thermal shock cycling. During the cooling phase after chip attachment, the warpage simulation results (0.398 mm) showed agreement with the measured data (0.393 mm), indicating robust mechanical stability of the primary interconnects (chip to glass substrate). Further thermal shock cycling tests demonstrated that the daisy-chain resistance change remained below the 20% failure threshold after 2000 cycles, as shown in Fig. 20, which indicates the long-term reliability of the BGA solder joints under thermal shock. Moreover, finite element simulation was used to analyze the stress-strain response of the solder joints in the x–x, y–y, and x–y directions. The results revealed that shear deformation (x–y direction) is the dominant mechanism leading to solder joint failure during thermal cycling. It should be noted that this study did not consider the impact of TGV and the lamination of multiple layers on the glass panel. In the actual manufacturing process, the dicing of glass substrates, the processing of TGV, and the fabrication of RDLs can all introduce reliability issues. During the dicing of glass substrates, three types of cracks may occur: cohesive cracking, interfacial delamination (between glass and RDL), and a three-stage cracking process (initiating from dicing defects, triggering interfacial delamination, and finally leading to internal glass cracking). Among these, cohesive cracking is the primary focus of research because interfacial delamination also occurs in organic substrates, and there are already some improvement methods for this type of crack. Cohesive cracking can be mitigated by solder resist pullback design and coating on the diced edges of the glass panel. The solder resist pullback design reduces the stress intensity near the crack tip by decreasing the solder resist thickness near the free edge, whereas the edge coating not only reduces stress but also inhibits moisture absorption by the glass.40 The density of TGV has a significant impact on the fracture strength of the glass panel. TSMC employed a four-point bending test to measure the fracture strength under different via pitches. The glass panel thickness was 360μm, the via diameter was 100μm, and the via pitches were 200, 300, 400, and 500μm, respectively. The results, as shown in Fig. 21, indicate that the fracture strength decreases as the via pitch narrows.41 This is because a higher via density reduces the effective cross-sectional area of the glass. However, simultaneously, a higher TGV density increases the effective CTE of the glass core, leading to better CTE matching between the glass core and the RDL. This trade-off requires careful consideration. In addition, the inherent brittleness of glass limits the number of RDLs, as the increased stress from additional layers may exacerbate reliability risks.

There are two options for selecting CPO optical interconnects: one based on vertical cavity surface emitting lasers (VCSELs) and the other based on silicon photonics (Si-Ph).42 VCSEL scheme has low cost, low power consumption, and easy integration; it does not require additional external light sources, and modulation is relatively simple. The coupling between the VCSEL and the external optical fiber belongs to surface coupling, which has a large coupling tolerance and high coupling efficiency and is suitable for short-distance transmission scenarios. The silicon photonics solution is compatible with CMOS processes, has high bandwidth (such as 110 GHz43), low optical loss in common communication bands (O-band, C-band), supports single-mode transmission, and is suitable for long-distance transmission, making it an ideal technology for implementing CPO.44 However, silicon photonics solutions face two major manufacturing challenges: first, silicon itself cannot emit light, which is generally solved using external laser sources or through heterogeneous integration.3^,45 Second, to achieve high-density optical I/O required for CPO, efficient and low-loss optical coupling is crucial. At present, the main optical coupling schemes include grating coupling and edge coupling. Grating couplers can achieve vertical coupling with large coupling tolerances, but they have high polarization sensitivity and low bandwidth. The edge coupling method aligns the optical fiber directly with the edge of the chip, which has high bandwidth and low loss. However, due to the mismatch between the optical fiber and the silicon chip mode field, the coupling loss increases, and the coupling tolerance is also low. To improve the coupling quality, tapered waveguide structures and V-shaped grooves are also used for edge coupling, mode field conversion, and passive alignment.44^,45 Corning proposed a new optical coupling scheme: firstly, the mechanical alignment between the optical fiber and the glass waveguides is achieved through a guide pin, achieving low-loss coupling in the first step, and then coupling from the optical waveguides to the silicon chip through adiabatic evanescent coupling. This method transfers the optical coupling from the chip to the glass plate, and the passive alignment of the optical fibers and glass waveguides improves the coupling accuracy and mechanical stability. The adiabatic evanescent coupling has low optical loss, and the half-loop insertion loss of this coupling structure is 1.7 dB.6 Corning’s solution not only solves the challenge of optical coupling but also demonstrates the potential of glass optical waveguides in CPO optical interconnect applications, where the fabrication of optical waveguide structures is the foundation for efficient optical interconnects.

The transmission of light in optical waveguides is based on the principle of total internal reflection (TIR): light enters a low refractive index material from a high refractive index material, and when the incident angle is greater than or equal to the critical angle, the light will undergo total reflection at the interface between the two materials. Therefore, the refractive index of the waveguides core layer must be higher than that of the cladding or substrate, that is, ncore>nclad or ncore>nsub. The optical confinement capability of an optical waveguide is determined by the refractive index difference Δn. The equation for Δn is Δn=ncore−ncladncore.(1)

The refractive index difference of a single-mode fiber is relatively small, with a typical value of 0.36% (SMF-28), whereas the refractive index difference on a PIC is typically greater than 40%. As a coupling structure between them, polymer optical waveguides often adopt a compromise of medium index contrast (Δn≈5%) to target a compact bending radius of approximately 100μm.15 By contrast, IOX glass waveguides utilize a low index contrast (Δn≈0.005). Although this low-contrast design results in a larger bending radius (typically 20 to 30 mm), its advantage lies in enabling highly efficient coupling to optical fibers. Regarding the mode mismatch with high-contrast photonic chips, research has demonstrated that it can be effectively compensated by designing evanescent couplers, which can achieve low coupling loss.44 As mentioned in Sec. 2, optical waveguides on glass can be made of polymers, but polymers have significant losses in common communication bands. Optical waveguides fabrication technologies based on glass itself include proton implantation technology, femtosecond laser technology, sol-gel technology, IOX technology, etc.46 These technologies each have their own characteristics, but there are certain limitations. When proton injection technology is used to prepare optical waveguides, it is necessary to fabricate them on a specific type of glass (such as oxyfluoride glass) and form the waveguides through the collision of high-energy ions with the glass. This type of waveguide is a barrier-type waveguide, where the refractive index of the waveguide layer slightly decreases (−0.49%), but the refractive index at the end of the ion path decreases significantly (−1.31%). Therefore, the light is confined to the waveguide layer, and subsequent annealing is needed to optimize its performance.47 Femtosecond laser technology also requires the fabrication of specific types of glass (such as Yb+-doped phosphate glass). This technology uses laser etching to etch a circle of damaged lines as a cladding (refractive index 1.51), and the light is confined to the area without laser modification (refractive index 1.52). This special material is hard and brittle and is prone to structural damage during the manufacturing process.48 The sol-gel method can be made on common glass. It uses the sol-gel method to make a layer of high refractive index film on the low refractive index glass as the waveguide layer (1.54 to 1.59), and then a layer of low refractive index film (1.51) is covered on the waveguide layer, realizing distributed feedback (DFB) laser transmission. However, its preparation process requires multiple spin coating and heat treatment, and the thin film thickness leads to easy spalling and cracking under thermal stress.49 Among the references discussing the three aforementioned technologies, proton implantation technology has validated the feasibility of fabricating waveguides in oxyfluoride glass, with studies indicating its potential for application in photonic integrated devices. Sol-gel technology has demonstrated the fabrication of a thin-film distributed feedback laser on a glass substrate, serving as an example of a functional integrated optoelectronic device. Femtosecond laser technology presents an instance of waveguide fabrication capable of complex light-field manipulation within Yb-doped phosphate glass, highlighting its potential in the field of glass-based integrated circuits. It should be noted that none of these three technologies has yet practically demonstrated the application of glass waveguides in CPO, which may be attributed to factors such as material specificity, process complexity, or challenges in achieving low-loss, high-volume manufacturing on common substrates. By contrast, ion exchange technology offers simple equipment and mature processes, enabling the fabrication of low-loss, high-performance optical waveguides on conventional alkali glass without requiring special treatment. As a result, it has become the most commonly used and suitable waveguide fabrication method for CPO applications to date.46 Corning’s optical waveguide fabrication is also based on IOX technology. As mentioned in the second part of the previous text, replacing alkali metal ions with other ions is the basis for forming optical waveguides. In integrated photonics, ion exchange technology mainly uses Ag+ to replace Na+ or K+ in glass. The change in composition will cause a change in refractive index, and the refractive index increases in the ion exchange region, so light is confined to this region. There are three ways to prepare surface waveguides: thermal diffusion method, electric field-assisted thermal diffusion, and electrolytic silver film. The process flow of thermal diffusion is as follows: glass is patterned through a mask and immersed in a nitrate melt containing Ag+ and glass ions (Na+, K+), and ion exchange is completed through thermal diffusion to form a surface waveguide, as shown in Fig. 22(a). The process of electric field-assisted thermal diffusion is similar to the above, but the difference is that the application of an electric field accelerates ion diffusion, which can easily form metal clusters and affect the optical waveguide performance, as shown in Fig. 22(b). Electrolytic silver film method: Solid silver film is used as the ion source to generate Ag+ through electrolysis for exchange, as shown in Fig. 22(c). Due to the susceptibility of surface optical waveguides to interference, postprocessing techniques are required to embed them inside glass. There are two main embedding processes: one is to immerse glass with surface waveguides in molten salt containing glass ions for reverse ion exchange and push the waveguides into a depth of about 1−2μm. Another method is to use an electric field for auxiliary embedding, which can make the waveguides buried deeper, as shown in Fig. 23.11 The process parameters of IOX (processing time, processing temperature, concentration of Ag+ in molten salt, etc.) and the composition of the glass (e.g., concentration of alkali ions) can all affect the refractive index contrast of the optical waveguides, thereby affecting its performance.44 At present, the production of optical waveguides using IOX technology is mainly based on wafer-level processes and can also be extended to panel level.50 In a study conducted by Corning in 2025, they developed high-performance integrated optical waveguides suitable for CPO application scenarios. This optical waveguide is fabricated using two-step IOX technology on high-purity alkali glass with special characteristics. The previous passive alignment and evanescent coupling methods6 are used for optical coupling. The special glass has a lower silver ion diffusion rate (less than 1×10−21m/s2), which solves the performance degradation problem caused by ion migration in existing commercial IOX glasses. The optical waveguides can work stably for five years at 85°C. In terms of optical performance, the propagation loss of the optical waveguides at 1310 nm is 0.034dB/cm, the bending loss is less than 0.1dB/cm, and its coupling loss with PIC’s SiN waveguides is less than 1 dB, with a coupling tolerance of 3−4μm.44

In terms of glass substrate applications for CPO, Corning has always been at the forefront. As mentioned in the introduction, Corning proposed the concept of optoelectronic hybrid glass interlayer in 2021. In this literature, as shown in Fig. 24(a), Corning fabricated optical interconnect structures with passive alignment of optical waveguides and optical fibers on two glass plates, as well as electrical interconnect structures containing cavities and TGVs. The connection loss between optical fibers and waveguides was tested, and the coupling structure between optical waveguides and optical chips was simulated through models.7 At the OFC in 2022, as shown in Fig. 24(b), Corning fabricated the optical waveguides involved in the optical interconnect structure and the cavity, TGV involved in the electrical interconnect structure on the same substrate, and bonded the PIC chip to the glass optical waveguides for coupling testing.6 In the OFC of 2025, as shown in Fig. 24(c), Corning focuses on the challenge of creating high-precision electrical interconnect structures within concave cavities and addresses the issues of spray coating LDI; the optimization of electroplating, and other processes has achieved circuit patterns with L/S<5μm at the bottom of the cavity.17 In another OFC paper in 2025, as shown in Fig. 24(d), Corning reported an independent optical interconnect structure that also integrates functions such as passive alignment of optical fibers, fan-out of optical waveguides, and evanescent coupling between waveguides and optical chips, which can be used in future CPO scenarios with ASIC chips.51 The low dielectric constant and low dielectric loss of glass enable its use in high-speed electrical interconnections, whereas its wide spectral transparency, low optical loss, and tunable refractive index make it suitable for optical interconnections. These inherent properties render glass naturally applicable to CPO scenarios, which is precisely the opportunity Corning has targeted. Corning’s research path follows a phased approach: first, separately validating the feasibility of electrical and optical interconnection structures on glass substrates; then, verifying the integration of both structures on the same glass panel; followed by independent optimization of each structure. In terms of optical interconnection, efforts have focused on reducing insertion loss and coupling loss. For electrical interconnection, process challenges in fabricating high-precision electrical interconnect structures have been addressed. Corning continues to optimize the performance of electro-optical integrated structures and is advancing their scalability to panel-level manufacturing.

The MOTION co-packaged optical transceiver technology developed by IBM demonstrates the tremendous potential of glass as a CPO substrate. Its core lies in utilizing the glass substrate as a common carrier for both electrical and optical interconnects, providing a practical and feasible solution to the common challenges faced by CPO, such as high-density integration, signal integrity, thermal management, and reliability. The key innovation of the MOTION technology is the realization of electro-optical integration. Its core chips (transmitter/receiver ICs), VCSEL lasers, and photodiodes are directly flip-chip integrated onto a single glass substrate. This approach fully leverages the advantages of glass in electrical interconnection, providing excellent channel quality for MOTION to achieve 50Gbps/ch high-speed signal transmission, effectively reducing signal delay and loss, which forms the foundation for the total 800 Gbps bandwidth,52 as shown in Fig. 25. IBM MOTION’s technical path (using 940 nm VCSELs) is highly compatible with the optical properties of glass, allowing for the possibility of achieving higher-density optical interconnects on the same substrate in the future (i.e., the electro-optical hybrid integration scheme proposed by Corning). Compared with pluggable solutions, the glass substrate process can support the soldering of optical engines directly onto the substrate, resulting in a smaller footprint, better signal integrity, and lower cost.

The manufacturing of the MOTION module relies on advanced packaging processes such as TGV and RDL, which are compatible with mainstream advanced packaging technologies and are precisely the core of glass substrate technology. Achieving vertical interconnects through TGVs can significantly enhance wiring density and integration levels. The success of MOTION validates the feasibility of glass substrates as interposers. In the future, CPO optical interconnects can either continue using the approach adopted by MOTION—via spatial optical paths or edge coupling—or be upgraded to the scheme demonstrated by Corning, which involves direct integration of optical waveguides on the glass substrate, enabling a higher-density “optical network.”

In September 2023, Intel announced a major breakthrough in glass substrate technology, aiming to provide a core solution for next-generation advanced packaging beyond 2030, particularly for high-density CPO systems. Intel showcased the first fully functional glass substrate test chip and plans to move into large-scale production between 2026 and 2030, with the goal of integrating 1 trillion transistors within a single package by 2030. Intel expects that glass substrates can achieve a 10-fold increase in interconnect density, supporting the connection of more transistors and chiplets within a single package; enable 50% larger chip package sizes (e.g., 24cm×24cm) to facilitate heterogeneous integration and support larger-scale system-in-package; reduce pattern distortion by 50%; support the embedding of passive components and optical interconnects to improve high-speed signal quality; and provide superior power delivery solutions. Intel has also pointed out challenges on the path to commercializing glass substrates: the current manufacturing and packaging costs of glass substrates are significantly higher than those of mature organic substrates; the glass substrate process faces challenges in yield ramp-up; there is a need to establish a complete supply chain ecosystem, including glass handling equipment, material suppliers, and testing and assembly services; and the brittleness of glass presents manufacturing difficulties, such as reliably drilling and routing, preventing edge chipping, precisely dicing large glass panels, and ensuring safe handling within factories.

The following Table 4 compares the CPO solutions from three companies across multiple dimensions. This table highlights their differentiated technological approaches: Corning focuses on the optical waveguide process platform, IBM is dedicated to the validation of VCSEL-based transceiver modules, while Intel prioritizes the development of a future system-level packaging roadmap. Despite the distinct technical routes taken by Corning, IBM, Intel, etc. The industry-wide adoption of glass substrates for CPO faces a common hurdle: the lack of unified standards. As international research intensifies, establishing standardization becomes critical to bridge the gap between prototypes and mass production. For instance, it is necessary to establish standardized testing methods for glass materials (e.g., for electrical and optical properties) to ensure the comparability and reliability of subsequent test results of the glass components; similarly, unified reliability testing methods and requirements are also needed to systematically enhance the feasibility of applying glass in CPO. Collaborative efforts through organizations such as the optical internetworking forum (OIF) will be essential to cultivate a robust ecosystem where material suppliers, packaging houses, and system integrators can synergize effectively.

Glass materials are currently a major research focus. Compared with organic and silicon substrates, glass exhibits superior electrical properties, surface flatness, and optical characteristics. In the face of rapid developments in AI and HPC, traditional pluggable optical modules are struggling to meet the rapidly growing application demands. CPO places the optical engine and the switch ASIC on the same substrate, bringing them closer together, which enhances high-speed signal integrity and reduces power consumption. The realization of CPO requires large-scale advanced packaging integration technologies, driving glass to become a key solution. Electrical structures fabricated based on glass materials, such as TGVs and RDLs, can meet current demands for interconnect density and bandwidth. Meanwhile, in terms of optical structures, the optical waveguides produced by Corning based on IOX technology exhibit low loss (propagation loss and coupling loss). In the application of glass substrates for CPO, Corning continues to dedicate efforts to integration research based on silicon photonics solutions, while IBM has demonstrated the excellent performance of a VCSEL-based CPO solution in terms of high speed and low loss. In the future, as CPO integration density continues to increase, the demand for glass substrates will become more urgent. Therefore, it is necessary to address challenges such as implementing CPO co-packaging architectures on glass, enabling photoelectric co-design, and developing compatible fabrication processes. This will further broaden the application prospects of glass substrates in the CPO field.

Acknowledgment. This work was supported by the Beijing Municipal Science and Technology Project (No. Z241100004224020) for CPO packaging research.

Xin Chen is a master’s student at the Institute of Microelectronics of the Chinese Academy of Sciences, China. Her research focuses on high-density interconnect integration technology for co-packaged optics (CPO).

Bohui Gao is a master’s student at the Institute of Microelectronics of the Chinese Academy of Sciences, China. His research focuses on key technologies of optical engines based on hybrid bonding.

Zhixin Sheng is a master’s student at the Institute of Microelectronics of the Chinese Academy of Sciences, China. His research focuses on VCSEL-based optical coupling for co-packaged optics (CPO) applications.

Xiaomeng Wu received his PhD from the University of Chinese Academy of Sciences, China. She is an associate researcher at the Institute of Microelectronics of the Chinese Academy of Sciences, China. Her research focuses on glass-substrate-based advanced packaging for heterogeneous integration, emphasizing process–structure–reliability co-design and high-density interconnect integration for next-generation microelectronic systems.

Huimin He received her BS degree in microelectronics from the Xi'an University of Post and Telecommunications, Xi’an, China, in 2012, and her PhD in microelectronics and solid-state electronics from the Institute of Microelectronics (IME), Chinese Academy of Sciences (CAS), China, in 2017. Since 2012, she has been an associate researcher in the System Packaging and Integration Research Center, IME, CAS. Her research interests include the advanced packaging of optoelectronic systems, signal integrity, and power integrity of high-speed signals.

Haiyun Xue received her PhD from the Institute of Semiconductors, Chinese Academy of Sciences, China. She is currently a professor with the Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, China. Her research fields include high-speed, high-density optoelectronic integration and 3D packaging technology.