As global data traffic continues to surge—driven by emerging applications such as artificial intelligence (AI), autonomous vehicles, and hyperscale data centers, optical communication has remained the cornerstone of high-capacity, long-distance data transmission, owing to its superior bandwidth and low-loss characteristics. Since the inception of low-loss optical fiber, pluggable transceivers have become the industry standard for electro-optical conversion at the network edge. For many years, research efforts were primarily focused on enhancing the speed and integration level of these discrete optical modules. However, as data rates have scaled beyond 800 Gbps per module, the electrical interconnects between front-panel optics and switch application-specific integrated circuits (ASICs) have emerged as a critical bottleneck. Limitations in the integrity of electrical signals, power consumption, and bandwidth density within traditional architectures have prompted a paradigm shift in optical system design. To address these challenges, copackaged optics (CPO) has been proposed as a promising integration strategy that places optical engines (OEs) close to electrical processing units, such as switch ASICs or AI accelerators, on a common package substrate. By significantly reducing the electrical link length, CPO improves energy efficiency, reduces latency, and enables higher bandwidth density. A growing number of companies and research institutes, including Intel,1 Ayar Labs,2 Ranovus,3 IBM,4 Marvell,5 Rockley Photonics,6 Cisco,7 Ruijie Networks,8 Broadcom,9 IME,10 and TSMC,11 have invested heavily in the development of CPO-based optical interconnects, positioning the technology as a cornerstone for next-generation data center and high-performance computing networks.

Despite its promising potential, CPO introduces significant thermal management challenges that remain insufficiently addressed in current architectures. Unlike conventional pluggable optics, where optical transceivers are thermally isolated from high-power ASICs, CPO integrates thermally sensitive photonic components, such as lasers and microring resonators, in close proximity to high-power compute die (referred to as XPU, which may be a switch ASIC, CPU, GPU, or AI accelerator). This proximity leads to elevated junction temperatures, increased thermal coupling, and new reliability risks, which must be addressed through co-optimized thermal design. Moreover, the fragmented nature of the CPO development ecosystem, where electrical, optical, and packaging engineers often work in isolation, has limited system-level understanding. For example, optical researchers may underestimate the mechanical and thermal implications of advanced packaging processes, while packaging engineers may lack insight into the temperature-dependent behavior of photonic components.

To bridge this gap, this paper provides a comprehensive review of thermal management in CPO modules, ranging from the integration of thermally sensitive photonic devices to package- and module-level thermal management. We begin with an overview of representative CPO architectures and power distribution, highlighting the architectural evolution from conventional electrical-only packaging and pluggable optical modules toward tightly integrated OEs copackaged with high-power ASICs (Sec. 2). Section 3 details laser integration and thermal management, covering various integration schemes and two main approaches to ensure temperature-stable laser operation: uncooled high-temperature lasers and thermoelectric coolers (TECs). Section 4 discusses the fiber array unit (FAU) assembly and the thermal stability of optical coupling efficiency. Section 5 discusses chip- and package-level thermal engineering strategies. Furthermore, Sec. 6 reviews thermal interface materials (TIMs) and module-level cooling strategies, including air-cooled and liquid-cooling solutions. Sections 7 and 8 provide future perspectives and conclusions on thermal codesign for next-generation optical interconnects.

The evolution from pluggable optics to CPO has been primarily driven by the need to reduce radio frequency (RF) loss and power consumption. As summarized in Fig. 1, pluggable optical modules exhibit relatively low power density, but the long electrical paths between the host ASIC and the OE lead to significant insertion loss and limited bandwidth scalability. On-board optics (OBO)12 and near-package optics (NPO)8^,13 mitigate these issues by shortening interconnects and improving power efficiency, yet thermal management remains at the board level. By contrast, CPO integrates OEs directly with an ASIC on a common substrate,14^,15 thereby minimizing the interconnect length and RF loss. However, the high-power density in CPO poses a significant challenge for thermal management. Looking beyond conventional CPO, emerging concepts involve co-packaging ASICs and OEs on an interposer, as discussed by NVIDIA16 and TSMC,17 are expected to further increase power density.

The architecture of CPO fundamentally determines thermal paths, interconnect lengths, and integration density, all of which are critical to thermal management. Over the past decade, both academia and industry have explored a variety of CPO architectures, distinguished primarily by the spatial organization of photonic and electronic components. Depending on the stacking strategy between the electronic integrated circuits (EICs) and the photonic integrated circuits (PICs), these architectures are generally classified into four categories: 2D, 2.5D, 3D heterogeneous integration (3D HI), and 3D monolithic integration (3D MI).

2D Packaging integrates PICs, EICs, and ASICs side-by-side on a shared substrate, as demonstrated in early CPO prototypes.18 This lateral configuration simplifies assembly and naturally separates heat-generating EICs from thermally sensitive PICs, facilitating basic thermal partitioning. Reported implementations include Intel’s wire-bonded scheme, achieving 4×64Gb/s at 1.3pJ/bit,19 Acacia’s flip-chip architecture on LTCC substrates,20 and Corning’s glass-based platform with through-glass vias (TGVs) and metal redistribution layers (RDLs).21 More advanced fan-out wafer-level packaging (FOWLP) approaches22^,23 enable finer interconnects and improved form factors. Conventional wire bonding faces parasitic and reliability challenges,24^,25 whereas flip-chip and FOWLP provide more mechanical robustness.

2.5D Packaging places PICs and EICs on an interposer, enabling short interconnects and improved signal integrity.4^,26^,27 From a thermal perspective, different interposer materials present distinct trade-offs. Organic interposers26^,28^–30 are cost-effective but limited by low interconnect density and restricted bandwidth. Silicon interposers support ultra-high-density routing and provide superior thermal conductivity (k), yet they suffer from significant RF loss and pronounced thermal crosstalk between the PIC and EIC.27 By contrast, glass interposers offer a compelling balance, featuring excellent CTE matching with substrates, suppressed thermal crosstalk due to moderate conductivity, and high plane-level scalability for large-scale integration.4^,31^–33

3D HI leverages heterogeneous integration to vertically stack PICs and EICs, thereby minimizing interconnect lengths and enhancing bandwidth density. 3D HI can be divided into TSV-based and TSV-free approaches. TSV-based schemes involve through-silicon vias (TSVs) either on an electronic die (E-TSV)34 or a photonic die (P-TSV)5^,35^–38 that offer the benefit of vertical thermal paths while posing additional challenges. The E-TSV approaches force heat from EICs through PICs, increasing thermal crosstalk and reducing photonic performance. By localizing TSVs in PICs, P-TSV designs enable direct contact between EICs and heat sinks, thereby providing more stable thermal performance and better scalability. TSV-free approaches, such as wire bonding, PIC embedding, FOWLP, and copper/dielectric hybrid bonding, can simplify fabrication by eliminating costly and process-intensive TSV integration, whereas their thermal dissipation paths depend strongly on the packaging method. Wire bonding39^–42 suffers from long electrical interconnects, whereas PIC embedding on organic or glass substrates improves compactness but still faces limited thermal conductivity.43^–46 FOWLP provides better thermal spreading through a thin epoxy molding layer and RDLs.6^,7^,9^,47 Hybrid bonding (e.g., TSMC COUPE, SoIC) facilitates bumpless vertical integration, effectively minimizing both electrical interconnect lengths and thermal conduction paths.11^,48

3D monolithic EPICs integrate photonic and electronic devices on a single CMOS chip, demonstrated by MIT and UC Berkeley with a data rate of 10Gb/s49^,50 and further advanced by GlobalFoundries with a 300-mm platform and wafer-scale laser integration.51^–53 Industrial efforts such as Intel–Ayar Labs’ TeraPHY2^,54 and Ranovus–AMD’s Odin engine3 highlight its scalability.

Understanding the power sources and their distribution within CPO modules is essential for effective thermal management. A typical CPO module consists of an ASIC, OEs, and optionally, digital signal processors (DSPs) to handle signal integrity. The OEs include drivers, transimpedance amplifiers (TIAs), PICs, and integrated light sources (ILSs). Owing to the high power consumption of DSPs, linear drive pluggable optics (LPO), which eliminates discrete DSPs, can effectively reduce overall power consumption. For instance, Broadcom’s Tomahawk 5 supports LPO interconnections.55 Therefore, the power distribution analysis in this section is based on a DSP-free 51.2 Tbps CPO architecture.

As illustrated in Fig. 2(a), the CPO module integrates a 51.2-Tbps Tomahawk5 ASIC with a power consumption of 835 W,8 surrounded by sixteen 3.2-Tbps OEs on the same substrate, each dissipating 19.7 W. The ASIC power is concentrated in a relatively small central area of 31.37mm×24.74mm. Each OE comprises 32 channels, each transmitting 100 Gbps PAM4 signals and comprising a driver, a TIA, and a bias-control heater for modulator biasing. Among the various integration approaches for OEs, monolithic integration is considered one of the promising directions for future development. Accordingly, we adopt the power values reported for monolithically integrated OEs as references. Specifically, the power consumption is 312mW/ch for drivers,52114mW/ch for TIAs,52 and 21.7mW/ch for heaters.56 The heater power is estimated from the average phase-shifter power per π phase shift (Pπ), but in practical control scenarios, the actual heater power consumption is typically lower. The laser power is calculated from hybrid ILS, with each laser dissipating 333 mW and supplying two optical channels. Thus, 16 ILSs are required for a single OE.57 As shown in the pie chart in Fig. 2(b), the 16 OEs collectively account for 27.4% of the total power of the CPO module. Within each OE, drivers and TIAs dominate with 69.4% of the power, whereas lasers contribute 27.1% and heaters only 3.5%. These power distributions reveal highly localized and heterogeneous heat sources within CPO modules. When combined with the close physical proximity and shared thermal paths between ASICs and OEs, such nonuniform thermal loads inevitably give rise to strong thermal coupling and crosstalk, motivating a detailed analysis of their impact on device-level thermal sensitivities in the following section.

The heterogeneous integration of high-power ASICs and sensitive optical components on a shared substrate inevitably leads to thermal crosstalk. As illustrated in Fig. 3, a typical CPO module consists of EICs stacked on top of a PIC. Heat generated by the EICs, PICs, and the central ASIC is conducted through the package lid to the heatsink and further managed by module-level cooling strategies. The crosstalk can be classified into three major types: intra-PIC interactions between adjacent photonic devices on the same chip (CT1), EIC-to-PIC crosstalk arising from heat dissipation by drivers and TIAs (CT2), and ASIC-to-OE crosstalk due to the high power density of central ASICs affecting copackaged OEs (CT3). These interactions can cause laser wavelength drift, optical power reduction, microring resonance shifts, reduced modulation bandwidth, increased photodetector dark current, and overall degradation in link performance. Table 1 summarizes the maximum operating temperatures, dominant thermal constraints, and relative sensitivities of key CPO components.

Lasers exhibit the most stringent constraints, with typical maximum operating temperatures around 70°C to 85°C.58 Elevated operating temperatures result in wavelength drift, output power reduction, and accelerated aging.60 Reliability studies show that when lasers operate continuously at 75°C, the 5-year failure rate increases significantly compared with operation at 25°C, rising from ∼0.02% to about 0.8%.61 Consequently, lasers are widely recognized as the dominant failure source in optical modules, accounting for nearly 90% of reported optical module failures.62

PICs exhibit markedly different thermal sensitivities depending on the device type, particularly for the three core components considered here: Mach–Zehnder modulators (MZMs), microring modulators (MRMs), and photodetectors (PDs). The silicon PIN-based MZM exhibits relatively weak temperature dependence in dynamic performance, maintaining linear phase modulation, stable electro-optic bandwidth, and high energy efficiency over a wide operating temperature range from 25°C to 80°C.63 By contrast, resonant devices such as MRMs are inherently more temperature sensitive, as temperature-induced refractive index variations directly translate into resonance wavelength shifts, leading to significant performance degradation.64 For PDs, elevated temperatures increase the dark current, which can degrade eye diagrams and receiver sensitivity, thereby increasing the bit error rate (BER).65^,66 Unlike laser sources, non-resonant PIC components such as MZMs, PDs, and phase shifters show remarkable thermal stability. Reliability assessments indicate these devices can withstand a projected 10-year lifetime.67

EICs, including drivers and TIAs, typically tolerate junction temperatures up to 100°C.59 Temperature variations mainly affect microwave gain, linearity, and bandwidth. Circuit simulations have shown that increasing the temperature from 27°C to 90°C results in ∼2dB gain degradation in driver amplifiers.68 Experimental measurements on TIAs further report a reduction of transimpedance gain by about 10dBΩ when the temperature increases from 25°C to 85°C.69 Nevertheless, the performance degradation in EICs remains moderate and can be effectively mitigated through circuit-level techniques such as adaptive gain control70 and dynamic voltage scaling (DVS),71 which compensate for PVT (process, voltage, and temperature)-induced variations.

ASICs generally support higher junction temperatures, with typical maximum operating limits around 105°C.59 Their thermal constraints primarily originate from reduced carrier mobility, increased leakage current, and accelerated long-term reliability degradation rather than immediate functional failure. In practice, ASICs benefit from well-defined noise margins72 and system-level power management strategies, such as dynamic voltage and frequency scaling (DVFS) and activity or clock throttling,73 enabling temperature-aware power regulation. Although ASIC performance is comparatively less sensitive to temperature, their extremely high power density makes them the dominant heat source in CPO modules, thereby increasing the thermal load experienced by adjacent OEs.

The realization of CPO modules necessitates the heterogeneous integration of ASICs, EICs, PICs, and surface-mount devices (SMDs) onto a CPO substrate. Unlike conventional packaging, CPO architectures exhibit diverse material layouts, intricate stacking strategies, and ultra-high interconnect bandwidth, all of which impose stringent constraints on thermal design, particularly for lasers and FAU assemblies. Figure 4 presents a multidimensional comparison between traditional electrical-only ASIC packaging and CPO packaging, emphasizing the unique design paradigms introduced by OE integration.

Lasers are the primary reliability bottleneck in CPO, and their failures largely determine module lifetime due to the limited serviceability of co-packaged modules. Laser failures can be grouped into dynamic stability issues and long-term degradation mechanisms. Dynamic stability reflects the laser’s capability to maintain consistent performance despite fluctuations in ambient conditions, such as temperature and humidity. Key metrics for evaluating this stability include optical power, wavelength stability, and relative intensity noise (RIN). In single-wavelength, nonresonant systems, maintaining adequate optical power is generally sufficient to allow operation over a wide temperature range without active temperature control. By contrast, wavelength-division multiplexing (WDM) or microring resonator-based systems require tight control of both power and wavelength, making them highly sensitive to temperature fluctuations and RIN, which can degrade signal quality.

Long-term degradation is primarily driven by elevated operating temperatures. High temperature accelerates intrinsic failure mechanisms such as defect generation in the active region, nonradiative recombination, and threshold current increase.74^,75 It also lowers the catastrophic optical mirror damage (COMD) threshold at laser facets, especially in Al-containing III–V materials, creating a positive thermal feedback loop that can trigger sudden facet failure.62^,74 CTE mismatch between the laser chip and the mounting substrate induces thermomechanical stress, which promotes defect propagation and material degradation. Maintaining the stress level below ∼40MPa is therefore critical for long-term reliability.76 High temperatures further accelerate electrode and interface degradation through metal diffusion, electromigration, and interfacial defects while simultaneously reducing optical performance via gain degradation, thermal lensing, and increased internal loss.74^,75 These failure mechanisms establish stringent thermal constraints for lasers in CPO modules and motivate the exploration of laser integration architectures, active cooling, and high-temperature uncooled lasers, as discussed in the following sections.

Different types of lasers impose distinct thermal design requirements on a CPO module. External laser sources (ELSs) deliver light remotely through fibers, reducing local heat but requiring higher output power due to coupling losses. According to the OIF 3.2-Tb/s CPO specification, the optical budget must exceed 18.5 dB.15 By contrast, integrated light sources (ILSs) minimize coupling loss by copackaging lasers on a PIC, but impose more stringent requirements on both assembly processes and thermal management. Various ILS integration schemes have been demonstrated, including heteroepitaxial growth,77 direct78 and adhesive bonding,79 flip-chip bonding,5^,80 micro-transfer printing,81 and photonic wire bonding.82

Heteroepitaxial lasers, formed by growing III–V materials on silicon substrates, face challenges due to lattice and CTE mismatches, which can induce dislocations, delamination, and enhanced nonradiative recombination, thereby reducing efficiency and output power. To mitigate these effects, silicon surfaces are typically prepared with nucleation and buffer layers before depositing functional layers such as contacts, waveguide claddings, and active regions [Fig. 5(a)]. Additional strategies, including quantum dots (QDs) to suppress defects,83 thermal cycle annealing to relax residual strain,84 and dislocation filter layers (DFLs) to block threading dislocations,85^,86 further improve material quality and device reliability. As shown in Fig. 5(b), direct bonding of a III–V film onto a silicon photonic (SiPh) chip, relying on van der Waals forces or hydrogen bonding, can effectively mitigate lattice mismatch issues. However, wafer-to-wafer direct bonding is not well-suited for 200 or 300 mm silicon platforms for two main reasons. First, the maximum available diameter of InP-based epitaxial wafers is currently limited to about 100 mm.87 Second, III–V materials are required only in localized emitter and receiver regions, whereas most of the bonded III–V wafer would be removed during patterning, resulting in substantial material waste. As a result, collective die-level direct bonding offers a more scalable and cost-effective solution, such as the die-to-wafer bonding approach reported by CEA-Leti.78 Alternatively, adhesive bonding using an interlayer, such as benzocyclobutene (BCB), can relax the surface roughness requirements for bonding [Fig. 5(c)]. Flip-chip (FC) bonding, including thermocompression bonding (TCB)88 and solder-reflow bonding,5^,53^,80^,89 is widely used to integrate prefabricated III–V dies on SiPh chips [Fig. 5(d)]. Index-matching adhesives are often employed to enhance butt-coupling efficiency between the III and V waveguides and the silicon waveguides. For example, IMEC demonstrated AuSn-based bonding supplemented by a reflowable UV epoxy that simultaneously serves as an underfill and index-matching medium. This approach improves optical coupling while maintaining mechanical robustness, as verified through MSL1 humidity testing and repeated 260°C reflow cycles.80 Furthermore, laser-assisted local solder reflow has been adopted by GlobalFoundries53 and AIM Photonics89 to avoid thermal degradation of previously bonded III–V dies in die-to-wafer integration. Microtransfer printing (μTP) enables flexible integration of prefabricated III–V lasers onto SiPh using adhesives such as BCB [Fig. 5(e)], offering greater material flexibility than wafer bonding but limited alignment precision. IMEC and Ghent University are working to promote large-scale wafer-level applications of μTP.90^,91 It should be noted that both the adhesive bonding and the μTP suffer from the low thermal conductivity of BCB, which poses a significant challenge for effective heat management. As shown in Fig. 5(f), photonic wire bonding (PWB) employs two-photon polymerization to form free-form polymer waveguides that optically interconnect discrete laser dies and SiPh chips placed on a common substrate.82 However, the thermal and mechanical reliability of the polymer waveguide remains a significant challenge.

Currently, many CPO implementations adopt ELS, thereby avoiding the need for complex in-package temperature control modules. Even in systems employing MRMs or resonators, resonance wavelength drift can be compensated through thermal phase shifters.92^,93 By contrast, the integration of on-chip lasers in CPO modules represents a key development trend, for which effective thermal management becomes a critical requirement, particularly for on-chip optical comb sources and WDM OEs. Consequently, the development of innovative TECs with high-energy efficiency and compact form factors will be essential. As shown in Fig. 6(a), a TEC operates based on the Peltier effect, in which an electric current passing through the junction of two different conductors (e.g., Bi2Te3 and Cu) causes heat to be absorbed at one side and released at the other. The cold and hot sides of the TEC are determined by the direction of the applied current. The efficiency of a TEC is typically characterized by its coefficient of performance (COP), defined as the ratio of the heat removed by the TEC to the electrical power supplied to maintain a target temperature. Figures 6(b) and 6(c) illustrate possible TEC integration schemes in CPO.

In the first scheme, the cold side of the TEC is in direct contact with the PIC, enabling fast thermal feedback and rapid cooling [Fig. 6(b)]. However, this configuration complicates electrical interconnections between the OE and the ASIC. In addition, the hot side of the TEC lacks an efficient thermal dissipation path, and any temperature rise on the hot side reduces the COP. To solve the problem, substrate-integrated microthermoelectric coolers (SimTECs) fabricated in glass substrates have recently been proposed.94 As shown in Fig. 6(d), by leveraging the inherently low thermal conductivity of glass, SimTECs suppress undesired heat transfer between photonic and electronic components while maintaining compact form factors. The device structure employs glass vias that are partially filled with p- and n-type thermoelectric materials and partially with copper, thereby combining electrical interconnection and thermoelectric cooling within the same substrate. Finite-element modeling has demonstrated that SimTECs can achieve temperature gradient variations up to 6 times higher than equivalent free-standing micro-TEC pillars. In the second configuration [Fig. 6(c)], the TEC is mounted on the EIC, with its hot side in contact with the lid, thereby enhancing heat dissipation from the hot side. Nevertheless, this approach predominantly cools the EIC rather than the PIC, resulting in elevated PIC temperatures, slower thermal feedback, and reduced temperature monitoring accuracy. Owing to the high power consumption of the ASIC, both configurations further suffer from the thermal crosstalk of CT3, in which a fraction of heat from the ASIC propagates through the lid into the OE, thereby increasing the TEC cooling load. These challenges impose stringent demands on TEC cooling performance.

In conventional photonic chip packaging, discrete TECs are commonly employed to control the temperature of PICs. However, discrete TECs typically exhibit a low COP, which increases the overall power consumption of CPO modules. To enhance thermal control, multiple strategies have been explored. The thermal resistance near heat-generating devices, such as lasers, can be reduced by optimizing materials and structures, for example, replacing low-thermal-conductivity BCB and SiO2 layers with high-conductivity aluminum nitride (319W·m−1K−1), whose refractive index and thermal expansion are compatible with InP lasers.96 As shown in Fig. 6(e), localized micro-TEC (μTEC) integration around each laser enables direct cooling of heat sources, improving temperature regulation while maintaining high integration density and energy efficiency. When the cooled components consume less than 20% of total system power, μTEC-based solutions outperform conventional macroscale TECs.95 Complementary improvements in PID-based feedback control, including variable-domain97 and analog PID algorithms,98 double closed-loop systems,99^,100 and fuzzy PID controllers,101 have achieved temperature stability from 0.1°C down to as low as 0.005°C. Wang et al. integrated a thermistor into an H-bridge circuit to convert temperature signals into voltage signals (VRt) in real time, achieving ultra-high TEC temperature control precision down to 0.0005°C.102

Overall, thermoelectric cooling is not a universal requirement for CPO modules, particularly for architectures based on ELS or athermal photonic components. However, for high-bandwidth-density CPO implementations that require on-chip lasers or dense WDM OEs, active temperature regulation remains difficult to fully replace. In addition, the limited package space in CPO emphasizes the need for highly localized, energy-efficient TEC solutions.

Uncooled lasers eliminate the need for TECs, enabling simpler system design and a more compact package size, while significantly reducing power consumption. High-temperature operation of lasers typically leads to (i) reduced optical output power and (ii) emission wavelength drift.60 To mitigate power degradation, structural and material engineering strategies have been widely explored. Nakahara et al. demonstrated a submicron ridge localized buried heterostructure (SR-LBH), in which the optical mode is more effectively confined within the active region. As a result, the device supported 112Gb/s direct modulation at 85°C.103 Intel reported a heterogeneously integrated DFB laser with 40 mW output at 80°C.104 Wavelength measurements from four channels on a 300-mm wafer exhibit high uniformity over a temperature range of 0°C to 80°C, with a standard deviation of only 0.3 nm. Moreover, a heterogeneously integrated DFB laser of similar design has achieved 100Gb/s PAM4 error-free CPO operation under rapid thermal ramps of 45°C/min.105 In epitaxial engineering, UCSB introduced DFLs and trapping layers (TLs) into QD structures, achieving 3.5 mW output at 105°C with 1200 h stability.77 For MQW lasers, Johnson et al. reported a capped mesa buried heterostructure (CMBH), which achieved an output power of 75 mW at 75°C and exhibited a low RIN below −155 dB/Hz.57

Thermal drift is addressed either by device-level correction or system-level tolerance. McKenna et al. realized <±0.1nm stabilization across 25°C to 99°C using combined self-heating and resistive heating.106 At the system level, the Continuous-Wave Wavelength Division Multiplexing Multisource Agreement (CW-WDM MSA) defines an uncooled flexible wavelength grid, allowing ±5nm initial offset and ±2.5nm thermal variation, tracked and compensated by tunable elements,57 thereby removing the need for TECs. VCSELs, benefiting from short cavity length, have also shown strong thermal robustness. Xun et al. achieved lasing up to 190°C with 0.064nm/°C drift,107 whereas other groups reported stable lasing beyond 80°C at 894 nm108 and wafer-fused 1550 nm VCSELs above 85°C.109

Looking ahead, high-power uncooled lasers are poised to become a cornerstone of future optical interconnect and CPO modules. Their continued advancement will rely on innovations in device structure, epitaxial engineering, and advanced integration techniques to improve intrinsic thermal stability. Complementary wavelength stabilization strategies and adaptive WDM standards will further ensure the robustness of the CPO system. Table 2 summarizes the representative uncooled laser technologies discussed above, highlighting their structures, operating temperatures, and key performance metrics.

FAU packaging represents a key distinction between CPO and traditional electrical-only packaging. Although advanced CMOS chips can withstand temperatures well above 500°C,117 the practical limit for standard assembly is defined by JEDEC-qualified solder reflow at 260°C.118 However, the organic adhesives and precision alignment within FAUs often cannot survive such reflow temperatures. The thermal stability of optical coupling efficiency in FAU and the pigtail fiber pick-and-place equipment requirements impose additional constraints on the maximum assembly temperature, process sequence, and even the choice of electrical interconnects between OE and CPO substrates. The FAU assembly must ensure long-term reliability at 85°C and, depending on the process, may need to withstand full reflow conditions.

Depending on the relative timing of fiber attachment and solder reflow, the OE packaging can be classified as fiber-first and fiber-last. In fiber-first approaches, FAUs or optical coupling structures must tolerate solder reflow temperatures. By contrast, fiber-last flows attach fibers after soldering, avoiding high-temperature exposure to optical interfaces. Although effective at mitigating thermally induced misalignment between PICs and FAUs, fiber-last flows introduce potential contamination from solder residues, which can degrade coupling efficiency.119 Mitigation strategies include VOC-free fluxes,119^,120 fluxless soldering such as Au-Sn bonding,5^,121^,122 and protective structures such as IME’s deep-trench features.10 The fiber-first and fiber-last assembly strategies impose different constraints on OE–ASIC interconnect choices. Wire-bonded (WB) or socket-based OEs inherently avoid high-temperature exposure of FAUs, allowing early fiber attachment, known-good-die (KGD) screening, and improved repairability. Solder-based OE–ASIC interconnects offer higher routing density and consistent impedance, but require FAUs that can tolerate solder reflow.

In WB architectures, the OE is bonded to the substrate without exposure to high temperatures, allowing preattached fibers and KGD screening. For example, a 4×50Gbps CPO microsystem was realized by integrating the XPU, DSPs, and OEs on a common substrate (Fig. 7),123 with a DFB laser flip-chip bonded onto the PIC. This assembly avoided thermal degradation from reflow soldering and achieved excellent optical performance, with TDECQ below 1.6 dB, extinction ratio above 2.7 dB, and BER <1.64×10−5. Socket-based OEs similarly avoid high-temperature exposure, offering additional advantages such as flexible 2D LGA array connections, higher channel counts, and field-replaceable modules [Fig. 8(a)]. By contrast, solder-based OE–ASIC interconnects enable short interconnects and high-density routing with tightly controlled impedance [Fig. 8(b)], but impose strict thermal constraints on FAUs and optical assemblies. Conventional fiber arrays cannot tolerate solder reflow, as plastic ferrules deform and UV-curable adhesives thermally degrade, causing permanent misalignment and high coupling loss.124 Thermal insulation of MT ferrules can partially mitigate these effects,124 yet industrial practice increasingly favors detachable FAUs to decouple fiber attachment from high-temperature electrical assembly steps, supporting fiber-last workflows.21^,125^,126

Silicon V-grooves are one of the most mature and reliable solutions for passive fiber attachment in CPO packaging. As shown in Fig. 9(a), silicon V-grooves enable high-precision self-alignment for both direct fiber attachment and detachable interposer-based interfaces.125^,127 To eliminate reliability risks related to adhesives, adhesive-free implementations have also been demonstrated, such as U-groove alignment combined with laser-fusion bonding for direct fiber fixation.128

To relax the stringent alignment tolerances between PICs and FAUs, microlenses and optical interposers are widely adopted. Microlenses fabricated from glass,129^,130 thermoplastics,131 photoresists,132 and silicon11^,133 have been reported. Notably, IMEC133 and TSMC11 demonstrated silicon microlenses etched directly into silicon substrates, achieving compact two-dimensional optical fan-out while eliminating adhesive bonding. As shown in Fig. 9(b), such microlens-based approaches collimate light emitted from grating couplers and redirect it into multirow FAUs, thereby improving alignment tolerance, integration density, and long-term stability. In parallel, optical interposers fabricated from glass125 or polymer waveguides134 have been widely adopted and in some cases co-integrated with electrical interposers to enable compact electro-optical fan-out architectures.21^,46

Material selection is critical for maintaining stable optical coupling in these structures. For FAU packaging adhesives, the glass transition temperature Tg and CTE strongly influence the reliability. High CTE values exacerbate thermal misalignment, whereas a low Tg compromises high-temperature durability and leads to long-term positional instability. For instance, the EXTEM resin reported in Ref. 131 demonstrates submicron dimensional stability (<0.5μm) with a CTE of ∼50ppm/°C, yet remains susceptible to thermally induced stress and coating degradation during high-temperature processing. It yet still showed a 0.7-dB additional loss after PIC–lens packaging followed by reflow. By contrast, silicon, silicon dioxide, and glass offer excellent CTE matching with Si-based PICs, significantly reducing thermomechanical misalignment.

Thermally induced warpage–related misalignment between the FAU and edge coupler arrays must be carefully considered during packaging, particularly for high-channel-count architectures. In such configurations, even micron-scale deformation can lead to pronounced coupling degradation at the outer channels (Fig. 10). For typical edge couplers, an increase of ∼3dB in coupling loss occurs when the horizontal or vertical misalignment reaches 2.0μm.135 Finite-element simulations further indicate that silicon photonic interposers may exhibit optical-engine–level warpage as large as 60μm under lead-free solder reflow conditions with a peak temperature of 260°C. Experimental evidence corroborates this sensitivity: Hall et al. reported local PIC warpage up to 4.25μm in a multi-PIC package, leading to an additional ∼2.31dB coupling loss for central channels.136 Consequently, effective warpage control in FAU assembly requires CTE matching, symmetric packaging layouts, and minimization of high-temperature process steps.

Recent studies indicate that FAU packaging can achieve high thermal and mechanical robustness when appropriate alignment strategies and materials are employed. Reflow-compatible adhesives with enhanced thermal resistance have been developed.80^,131 Kurata et al. reported a high-reliability optical transceiver integrating a 1310-nm quantum-dot laser, grating couplers, and multimode fiber interfaces, maintaining optical output variation within 2 dB over −6°C to 120°C and demonstrating stable operation for more than 10 years at 100°C.137

The reliability of wafer-level fabricated alignment structures has also been validated under standardized qualification tests. GlobalFoundries demonstrated a FAU attachment based on 300-mm wafer-level V-groove self-alignment, showing insertion loss (IL) degradation below 0.3 dB after 1000 h of 85°C/85% RH humidity exposure and less than 0.2 dB variation over 500 thermal cycles from −40°C to 85°C, while also tolerating 260°C reflow processes.138^,139 Building on this, a monolithic platform integrating electrical and optical interconnects was demonstrated, showing stable FAU interconnects at 105°C.140 Intel further evaluated a 24-channel FAU attachment using V-groove self-alignment under more stringent conditions,124 finding that IL degradation remained below 0.22 dB per facet over three SAC reflow cycles or 1500 JEDEC thermal cycles from −55°C to 125°C, whereas 1008 h of high-temperature storage induced only 0.4 dB IL reduction. Unbiased highly accelerated stress testing (uHAST) revealed greater sample-to-sample variation (0.5 to 12.5 dB), indicating potential moisture-assisted degradation under extreme conditions.

Overall, these results demonstrate that modern FAU packaging, particularly V-groove approaches, provides robust thermal performance within typical operating ranges (−40°C to 85°C). Although silicon V-groove structures offer excellent reliability, they occupy significant chip area and increase cost, highlighting the need for more area- and cost-efficient solutions in the future. With the continual increase of SerDes rates of ASICs, solder-based OE–ASIC interconnects are becoming the dominant trend, which also increases repair complexity. Consequently, future FAU packaging is expected to rely on reflow-tolerant and detachable connector solutions to ensure long-term operational stability.

This section focuses on chip-level and package-level thermally induced performance degradation in CPO modules. As PICs scale toward large transceiver arrays with extensive phase tuning, localized heat generation and lateral heat spreading lead to pronounced thermal crosstalk and stability challenges. The following discussion reviews intrinsic mitigation approaches, including on-chip thermal isolation, heater and phase shifter design, and chip-level thermal modeling and compensation. Regarding package-level thermal considerations, this section evaluates the reliability of emerging glass substrates and polymeric waveguides.

Thermally induced phase crosstalk is one of the primary challenges in densely integrated PICs, particularly for large-scale transceiver (TR) arrays with thermal phase tuning calibration. To mitigate this problem, various strategies have been explored, including enhancing thermal isolation, reducing heat dissipation, and active temperature feedback control. A widely adopted method to suppress lateral heat spreading is the introduction of passive thermal isolation structures. As illustrated in Fig. 11(a), deep isolation trenches are commonly employed to interrupt in-plane heat conduction paths, enabling a reduction in the safe spacing between adjacent components by up to 80%.141 Further enhancement of thermal isolation can be achieved using full undercut structures [Fig. 11(b)], which provides near-complete thermal decoupling of active regions.142 The main drawback of isolation trenches or undercut techniques is the increased thermal resistance, which consequently slows the thermal response of the device. To mitigate this limitation, copper vias can be incorporated to enhance vertical heat conduction, resulting in a reported ∼30% reduction in thermal resistance and a device temperature decrease of 7.5°C.141 For applications requiring regional isolation rather than point isolation, ring-shaped deep trenches combined with metal rings have been proposed. As shown in Fig. 11(c), metal layers (M1, Via, M2) together with isolation trenches form a closed heat shield (CHS), effectively protecting the enclosed region from external thermal disturbances while maintaining fast thermal dynamics.143

Beyond structural isolation, reducing heat generation at the source is an effective means of mitigating thermal crosstalk. Conventional metallic heaters can be replaced or optimized using doped silicon heaters, which confine heat generation closer to the optical mode and reduce parasitic heat spreading. In Fig. 11(d), the metallic electrode layer (TiN/Al) acts as a heat spreader, effectively reducing the rise time and minimizing thermal crosstalk. As demonstrated by Iino et al.,144 their 7μm-long phase shifter achieved Pπ<20mW with a figure of merit (FOM) of 8.89mW·μs, and exhibited less than 1.6% phase crosstalk at a 30μm spacing. In Fig. 11(e), further thermal isolation is achieved by introducing deep trenches. Jacques et al.145 compared thermally induced phase crosstalk between adjacent waveguides spaced by 5μm, observing that TiN heaters exhibited a phase crosstalk of 15.9%, whereas N++ Si heaters reduced it to 12.7%, and N++ Si heaters combined with deep trenches further suppressed it to 3.5%.

For active photonic devices, isolation trenches have also been used to suppress carrier diffusion induced by thermal crosstalk of the heater. Appropriate thermal isolation has been shown to increase the quality factor of microring resonators.146 Because heaters are a major heat source in PICs, minimizing the use of thermal phase shifters is an effective approach to mitigate thermal crosstalk. As shown in Fig. 11(f), a titanium-doped indium oxide-gated MOSCAP can be used to realize electro-optic phase shifting. Based on this design, a silicon MRM achieves near-zero static power consumption, ranging from pW/nm to nW/nm, which is at least six orders of magnitude more power-efficient than conventional free-carrier injection or thermal tuning (mW/nm).147^,148 Thin-film lithium niobate (LNOI) modulators provide another nonthermal phase tuning paradigm by exploiting the Pockels effect.149 Compared with silicon, LNOI exhibits a substantially lower thermo-optic coefficient (<4.2×10−5K−1150 versus 1.8×10−4K−1 for silicon),151 resulting in reduced sensitivity to temperature fluctuations from both the environment and neighboring active components. Consequently, LNOI-based platforms exhibit enhanced thermal stability in densely integrated photonic systems. However, the relatively modest electro-optic interaction strength of lithium niobate necessitates extended modulation lengths, posing challenges for high-density integration. Advanced electrode designs, such as folded traveling-wave electrodes, have been introduced to reduce the VπL product.152 In addition, the passive nature of lithium niobate requires heterogeneous integration of light sources and photodetectors, increasing fabrication complexity. Despite these near-term hurdles in cost and scalability, TFLN remains a premier candidate for upcoming high-data-rate CPO systems, offering a unique combination of high-speed performance and exceptional thermal robustness.

For large-scale photonic arrays, chip-level thermal analysis and global compensation schemes are indispensable. Iino et al. proposed a strategy to mitigate thermal crosstalk in PICs by simultaneously controlling all thermal actuators according to the eigen solution of the coupled system, termed thermal eigenmode decomposition (TED).153 The technique was validated through numerical simulations and experiments on coupled microring resonators (MRRs) and Mach-Zehnder interferometer (MZI) switch fabrics. Compared with individual control of phase actuators, TED ensures convergence of tuning algorithms, reduces the number of iterations required, and is less sensitive to the initial state of the PIC.153^–155 For example, Gurses et al. experimentally demonstrated that using this method leads to significant improvements in crosstalk suppression and extinction ratio recovery in MZI arrays.154 This approach is general and can be applied to arbitrary PIC architectures. In summary, Table 3 provides an overview of the on-chip design strategies discussed above for mitigating thermal crosstalk.

Packaging-level thermal considerations focus on ensuring that all dies within a module operate within their allowable temperature windows, with particular attention to inter-die thermal crosstalk at both the CT2 and CT3 levels. In 3D-stacked OEs, PICs are exposed to severe CT2 thermal coupling, requiring better temperature robustness. By contrast, in 2.5D OEs, the use of low-thermal-conductivity interposers, such as organic or glass, can effectively mitigate thermal crosstalk between EICs and PICs. The CT3 thermal crosstalk between the ASIC and the OEs is another critical concern. OEs typically require a lower case temperature (below 85°C),58 whereas ASICs can operate at junction temperatures up to 105°C.59 There are two typical examples of CPO deployment scenarios: XPU with optical I/O54 and switch ASIC with discrete OEs.8 In ASIC + OE configurations, OEs are distributed along the extended shoreline of the ASIC to accommodate the quantity needed for total bandwidth. This layout enables the use of independent lids and heatsinks for the ASIC and OEs.8^,59^,157 Celestica reported that separate heatsinks can reduce the OE temperature by 2.2°C, at the cost of a 2.1°C increase in ASIC temperature, primarily due to the reduced effective heat-spreading area for the ASIC.8 More aggressive decoupling has been demonstrated using independent microchannel cooling, achieving ASIC and OE temperatures of 97.3°C and 31.3°C, respectively.157 Therefore, in cases involving separate heatsinks, the dominant design objective is minimizing the ASIC-side thermal resistance and maximizing heat exchange area. By contrast, XPU + optical I/O architectures typically place OEs in close proximity to the XPU, often under a shared lid and heatsink, resulting in strong thermal crosstalk and imposing more stringent temperature robustness requirements on the OEs. Regardless of architecture, larger substrates and more relaxed OE placement can reduce power density, thereby alleviating crosstalk. However, unconstrained scaling of substrate size or OE–ASIC separation is not feasible, as excessive distance degrades the integrity of electrical signals. Consequently, packaging-level thermal management in CPO must be co-optimized with electrical performance. In addition to heatsink and lid architectures, the thermal conductivity of the CPO substrate also affects the thermal crosstalk of CT3. Organic substrates remain the most mature solution but suffer from high-frequency loss and warpage. By contrast, glass substrates offer low CTE, low thermal conductivity, low dielectric loss, high-density TGVs, optical transparency, and compatibility with panel-level manufacturing and have therefore attracted growing research interest. Furthermore, polymer optical waveguides (PWGs) implemented on substrates as optical RDLs have been widely explored for substrate-level optical interconnects. Accordingly, the following discussion focuses on the thermal characteristics and reliability implications of these substrate and waveguide technologies.

Glass-based interposers have emerged as a promising platform for mitigating lateral thermal crosstalk due to their intrinsically low thermal conductivity [∼1 to 3W/(m·K)] and high structural design flexibility. Through ion-exchange processing, low-loss optical waveguides with propagation losses below 0.1dB/cm can be fabricated directly in glass substrates, whereas TGVs and RDLs enable high-density electrical interconnection between EICs and PICs.21 Experimental studies demonstrate that embedding glass bridge structures within silicon interposers enhances thermal isolation by ∼20% over an operating temperature range of 40°C to 120°C, yielding a maximum temperature difference of up to 17.0°C between neighboring chips.158 To further enhance thermal isolation, ultra-low thermal conductivity materials such as polyimide aerogels [∼0.029W/(m·K)] can be incorporated into die-embedded glass interposers, forming effective thermal barriers between high-power and temperature-sensitive components.159 In practical designs, the arrangement of TGVs and the thickness of the glass substrate must be carefully optimized to balance lateral thermal isolation with vertical heat dissipation.

PWGs are widely investigated as optical redistribution layers in CPO architectures owing to their low cost, simple fabrication, and large mode size that facilitates efficient fiber coupling. In this context, their ability to maintain stable optical propagation under thermal exposure is therefore a critical factor. A common issue associated with polymer waveguides is thermally induced aging, such as yellowing, which can increase optical absorption depending on polymer chemistry and environmental conditions.160 Despite these concerns, extensive studies on polymer platforms, including SU-8, fluorinated SU-8 (FSU-8), electro-optic (EO) polymers, and benzocyclobutene (BCB), have shown that these materials provide sufficient thermal stability to maintain optical performance. SU-8 waveguides have been shown to withstand solder reflow processes up to 300°C while maintaining low optical loss.161^,162 Fluorinated SU-8 (FSU-8) further improves optical absorption and thermal stability, with reported degradation temperatures around 366°C.163 Electro-optic polymers exhibit glass transition temperatures near 190°C and maintain stable performance after extended aging tests, such as 2000 h at 105°C.164^,165 Benzocyclobutene (BCB)-based waveguides demonstrate glass transition temperatures above 350°C and propagation losses as low as 0.68dB/cm.166^,167 A series of demonstrations by IBM using partially fluorinated168 and siloxane-based169 polymer waveguides further validate their long-term reliability and temperature compatibility with solder reflow processes. More recent results indicate that both “PWG-first” and “PWG-last” assembly flows can maintain chip–polymer–fiber insertion losses below 2.5 dB under JEDEC qualification testing.170 In addition, high optical power stability has been demonstrated, with polymer waveguides supporting continuous-wave operation up to +24.6dBm, confirming their suitability for external-laser-based CPO systems.171 Overall, although polymer waveguides are intrinsically more susceptible to thermal aging than inorganic dielectric waveguides, continued advances in material chemistry and process optimization have significantly improved the thermal stability of their optical propagation, supporting their growing adoption as optical redistribution layers in CPO packaging.

TIMs fill the gaps between chips and heat sinks, reducing overall thermal resistance. As shown in Fig. 12(a), conformally filling interfacial voids increases contact area and improves heat transfer, whereas Fig. 12(b) illustrates that temperature rise across the interface grows rapidly with increasing thermal interface resistance. For a 51.2 Tbps ASIC operating at a heat flux of 100W/cm2, a thermal resistance of 10mm2·K/W results in a temperature difference of ∼10K. From a thermophysical perspective, the fundamental performance requirements for TIMs, namely thermal conductivity, interfacial thermal resistance, and mechanical compliance, remain unchanged in CPO systems. The overall interface thermal resistance consists of the intrinsic bulk resistance of the TIM (Rbulk) and the contact resistances at the two interfaces (Rint1 and Rint2), as illustrated in Fig. 12(a). A wide range of TIM material systems have been developed for conventional electronic packaging,172 including polymer-based composites,173^,174 carbon-based materials,175^–178 metals and liquid-metal–based TIMs,179^,180 as well as two-dimensional (2D) materials.181^,182 These approaches collectively span effective thermal conductivities from a few W·m−1K−1 for polymer composites to over 200W·m−1K−1 for vertically aligned graphene structures. Although these material platforms were not specifically developed for CPO, they provide a useful reference for interface-level thermal design under CPO-specific constraints. In practice, TIMs in CPO modules are primarily applied at two interfaces (Fig. 3): the lid–heat sink interface, where conventional high-conductivity TIMs are generally sufficient, and the lid–chip interface, where additional constraints arise. At the latter interface, TIMs must be electrically insulating and optically compatible to avoid electrical short circuits and optical contamination.183 In this context, h-BN-based TIMs represent a potential option due to their intrinsic electrical insulation, with reported in-plane and through-plane thermal conductivities of 39.0 and 11.5W·m−1K−1, respectively.182 Currently, the industry lacks a universal TIM platform specifically synthesized for CPO. Instead, designers must still compromise by choosing different materials based on localized interface constraints.

As illustrated in Fig. 13, the increasing bandwidth of optical systems, from pluggable modules to OEs, switching ASICs, and CPOs, is accompanied by a steep rise in power consumption and power density. Specifically, power density rises from 0.01W/cm2 for a 400 Gbps pluggable transceiver to 100W/cm2 for a 51.2 Tbps ASIC.8 Future OEs are expected to be co-packaged with high-performance computing chips such as GPUs and GPU-HBM, which can exhibit projected power exceeding 1000 W and power densities above 100W/cm2.194^,195 High-power chips present significant thermal management challenges for CPO systems, including hotspot mitigation and overall cooling, and future designs with even higher power densities will require advanced liquid cooling. This section reviews representative cooling strategies for CPOs, discussing their operating principles, scalability, thermal efficiency, and performance improvement.

Conventional cooling strategies include passive and active mechanisms. Passive approaches use heat spreaders and finned heat sinks to dissipate heat via conduction, natural convection, and radiation without external assistance, typically employing high-conductivity materials such as copper (400W·m−1K−1), aluminum (238W·m−1K−1), silicon (130W·m−1K−1), or AlN ceramic (170W·m−1K−1). Phase-change materials (PCMs) provide transient thermal buffering via latent heat absorption,203 but low conductivity and phase instability limit their applicability.204 Forced-air cooling, which enhances convection via fans, is the most widely adopted method in conventional pluggable optical and external laser modules.112^,205 The maximum heat dissipation capacity of air cooling is about 55W/cm2 at a junction temperature of 100°C.196 For OEs that require a maximum junction temperature of 70°C, the allowable heat flux would be even lower. As shown in Fig. 13, with module power densities reaching 11W/cm2 for 3.2 Tbps OEs15 and over 100W/cm2 for 51.2 Tbps ASICs,8 air cooling faces significant challenges in managing localized hotspots and high heat fluxes in compact modules. Although some teams continue to develop 51.2 Tbps CPO systems that rely on air cooling,206 long-term thermal management for higher heat fluxes will require a transition to liquid cooling. For example, Zhang et al. reported that liquid cooling improved the heat dissipation capacity of a 30 W QSFP-DD module by 1.43× compared with air cooling.207

Liquid cooling has emerged as a leading solution, leveraging the superior thermal properties of liquids to efficiently dissipate high heat fluxes. Common approaches include cold plates, jet-impingement cooling, microchannel cooling, and immersion cooling. Many recent CPO systems, including 12.8,208 25.6,59 and 51.2 Tbps,8^,157^,209 have employed liquid cooling, demonstrating its effectiveness in managing their thermal loads. Furthermore, depending on whether a phase change occurs during the heat dissipation process, it can be divided into single-phase liquid cooling or two-phase liquid cooling. The following sections discuss the characteristics and recent advances of these representative techniques.

The inlet and outlet configurations of a cold plate directly influence the fluid flow characteristics and temperature distribution.213 Wu et al.157 used two independent heat sinks with liquid cold plates (4 LPM, 20°C) to cool a 51.2 Tbps CPO system with a 750 W ASIC and eight 64 W OEs, maintaining the ASIC junction temperature below 97.3°C and optical chips below 31.3°C, and demonstrating a cooling capability exceeding 179W/cm2 [Fig. 14(b)]. Beyond inlet/outlet positioning, the geometry of the microchannels, including cross-sectional shape and flow path design, also affects the cooling performance.213

While conventional cold plates provide uniform cooling, their ability to handle localized hotspots is limited. By contrast, jet impingement cooling offers significantly enhanced heat transfer at targeted regions, achieving a heat transfer coefficient (HTC) as high as 6.25×104W/(m2·K) with minimal pumping power of only 0.3 W.215 Polymer-based microjet coolers fabricated via 3D printing have been shown to cool dies as large as 23mm×23mm, dissipating ∼175W/cm2, with an ultra-low thermal resistance of 0.065K/W [Fig. 14(c)].210 Although 3D printing and low-cost polymers enable the realization of complex jet-cooling structures, limitations in fabrication precision, reliability, and thermal conductivity create challenges in balancing cost, complexity, and performance. Cui et al. reported that a hybrid slot jet impingement/microchannel heat sink fabricated from copper significantly enhances cooling performance, achieving a heat flux of up to 200W/cm2.216

In SPIC systems, the coolant remains in the liquid state while circulating to remove heat. The heat flux of SPIC can reach up to 152W/cm2.198 The cooling performance is primarily enhanced by increasing the heat exchange surface area and improving convective heat transfer efficiency. Common enhancement strategies include optimizing heat sink fin geometry, improving inlet/outlet configurations, and designing internal flow channels for more uniform distribution and enhanced flow disturbance.226^,227 Muneeshwaran et al.226 systematically analyzed the thermal performance of heat sinks with different inlet/outlet layouts and base structures, including solid, heat-pipe-embedded, and vapor chamber (VC) bases. Compared with conventional solid metal base, heat pipes and VC-based heat sinks reduced overall thermal resistance by ∼13% and 19%, respectively. Luiten et al.228 employed an aluminum finned vapor chamber heat sink under natural convection, achieving a heat flux of 22W/cm2. Under forced convection, a copper body-centered cubic lattice heat sink demonstrated a maximum cooling capacity of 66.7W/cm2.229

Compared with single-phase immersion cooling, which relies solely on liquid convection to remove heat, TPIC exploits the latent heat of vaporization to achieve significantly higher heat flux dissipation with lower temperature gradients. The low-boiling-point dielectric fluid vaporizes upon absorbing heat from the device surface, and the generated vapor condenses on the cooler region above the liquid surface, forming a natural circulation loop. Despite its high cooling potential, TPIC faces several technical challenges when integrated with high-density electronic and photonic packages. The main bottlenecks include limited boiling surface area, non-uniform vapor generation leading to dry-out, and unstable bubble dynamics. In addition, dielectric fluids generally exhibit low thermal conductivity, and their physical properties (e.g., surface tension, viscosity) strongly influence boiling initiation and rewetting behavior, making it difficult to sustain uniform nucleate boiling across large chip surfaces.

To overcome these limitations, recent studies have focused on enhancing both boiling and condensation heat transfer. Surface texturing and coatings have proven highly effective in promoting nucleation and liquid rewetting. As shown in Fig. 16(a), Si nanowires grown on Si micropillar arrays (SiNW/MP) achieved a critical heat flux (CHF) of (17.4±1.2)W/cm2 and an HTC of 23.6kW/(m2·K), corresponding to 30% and 455% improvements compared with plain SiO2.230 Femtosecond laser structured copper surfaces (Sa=0.38μm) achieved CHF values up to 93.5W/cm2.233 The combination of lotus-type copper and grooved geometries achieved a CHF of 534W/cm2 and an HTC of 126kW/(m2·K) in water, and 104W/cm2 with an HTCmax of 22.3kW/(m2·K) in FC-72, corresponding to 3.7× and 6.9× CHF enhancements compared with smooth surfaces.234 Furthermore, surface wettability modulation, such as anisotropic micropillar arrays of PDMS with hydrophilic SiO2-coated surfaces, has been shown to enhance the HTC by 63% [Fig. 16(b)].231 Under subcooled flow boiling conditions (ΔTsub=40K), this design achieved a CHF of 249W/cm2. Industrial demonstrations further verify the feasibility of TPIC for high-power packages. TSMC implemented a 900-W CoWoS high-performance computing (HPC) package cooled by TPIC, comparing solid-copper and vapor-chamber boiling modules [Figs. 16(c) and 16(d)].232 The vapor-chamber design exhibited a lower thermal resistance (0.0355°C/W) than the solid-Cu base (0.0542°C/W) owing to the larger effective boiling area, supporting a heat flux up to 200W/cm2. This confirms that TPIC can be effectively integrated into large-scale 2.5D or 3D packaged chips to meet the increasing power density demands. Looking ahead, future TPIC technologies are expected to evolve toward microstructured and hierarchical boiling interfaces, integrated vapor chambers within interposers or substrates, and closed-loop dielectric fluid systems. This evolution is driven by the need to enhance HTC and CHF, ensure uniform temperature distribution across high-power 2.5D/3D packaged chips. Combined with precise thermal-fluid modeling and advanced surface engineering, TPIC is poised to become a key enabler for next-generation high-power, high-bandwidth CPOs. Table 4 summarizes representative liquid cooling technologies reported in recent studies, including module type, TDP, heat flux, and key strategies across different cooling approaches.

Overall, efficient thermal management is fundamental to ensuring the performance and reliability of CPO systems. As discussed above, the nonuniform power distribution of high-power ASICs and GPUs can lead to severe thermal crosstalk, requiring careful floorplanning and heat spreading strategies. On-chip thermal design, incorporating temperature-insensitive components and thermal isolation trenches, provides an additional means to stabilize optical transmission in CPO systems. Furthermore, high-performance TIMs are essential to minimize interfacial resistance and maintain thermal uniformity between the stacked electrical and optical components. For next-generation CPO architectures that feature 3D integration of electrical and optical chips, on-chip light sources, and higher-power ASICs or GPUs, cold plate liquid cooling remains a feasible and effective approach. However, as power densities continue to rise, emerging cooling technologies such as two-phase liquid cooling and localized jet impingement should be considered to mitigate hotspot formation and enhance heat flux capability. In the longer term, integrating microchannel cooling directly within advanced packaging structures represents a promising direction, although it requires the development of reliable dielectric coolants and robust sealing technologies to ensure long-term reliability.

Future CPO developments will be driven by the increasing demand for higher bandwidth, power efficiency, and integration density. From device-level innovations to system-level thermal management, several promising directions are emerging.

For silicon photonic integrated chips, the integration of lasers capable of withstanding reflow temperatures, operating at high temperatures, and delivering high optical power is a key requirement. Heterogeneous integration and microtransfer printing are expected to remain dominant approaches for a considerable period. By contrast, research on heteroepitaxial lasers still faces challenges in performance, reliability, and cost, which must be addressed before large-scale adoption becomes feasible.

In the near term, OEs will employ bump, TSV, or FOWLP technologies. TSV approaches face cost constraints, whereas FOWLP must overcome challenges in high dielectric loss, thermal dissipation, and warpage control through optimized material and structural design. Thermal-induced warpage can lead to open-circuit failures and fiber array misalignment, which remain major reliability concerns. Research on reflow-tolerant optical connectors and high-temperature adhesives will continue to be critical. In the future, hybrid bonding, bump-based interconnections, and two-dimensional fiber array I/O using grating couplers and silicon microlenses will become key enablers for thermally stable and scalable optoelectronic interconnects. At the copackaging substrate level, in addition to conventional organic substrates, both silicon and glass interposers are considered promising platforms for next-generation CPO systems. Silicon interposers enable fine-pitch, ultrashort interconnects, making them highly attractive for compact CPO systems.16^,17 Nevertheless, due to silicon’s high thermal conductivity, careful thermal codesign is required to mitigate thermal crosstalk between the ASICs and OEs. This challenge becomes more critical when heat extraction from the silicon interposer to the host board is limited. Glass-based substrates offer advantages such as low dielectric loss, low warpage, and optical transparency. However, their widespread adoption will require further advances in mechanical robustness and reliable multilayer RDL fabrication processes. Currently, organic substrates remain the mainstream choice for CPO systems due to the mature organic substrate ecosystem. However, once the inherent brittleness of glass substrates and the challenges of multilayer RDL fabrication are fully resolved, they hold promise as a superior platform for next-generation CPO integration.

As data rates and operating power increase, MRMs have attracted growing attention due to their compact footprint, low drive voltage, and wavelength-selective operation, which enables their use in WDM systems. Although MRMs are highly sensitive to temperature and require tight fabrication tolerances, continued advances in process scaling, on-chip thermal isolation, and thermal compensation techniques are expected to improve their operational stability. Once thermal stability is achieved, MRMs are anticipated to play a crucial role in short-reach CPO transceivers.

Rising bandwidth and power density are redefining CPO thermal management architectures. Electrically nonconductive interface materials, such as polymer-based TIMs and h-BN, remain essential within CPO modules. Carbon-based and metallic TIMs may be used outside the CPO package where the risk of electrical shorting is negligible. Meanwhile, the scalable manufacturing and long-term reliability of 2D TIMs remain open challenges. In the long term, minimizing the number of thermal interfaces is fundamental to reducing overall thermal resistance. Therefore, cointegration of chips, substrates, and cooling structures through advanced packaging will be a defining trend. Although single-phase cold plates are becoming mainstream, two-phase dielectric liquid cooling and jet-assisted boiling technologies are expected to dominate in future high-power CPO modules.

This review systematically summarizes the thermal management challenges and emerging solutions in CPO. By analyzing representative CPO architectures, power distribution, and thermal coupling mechanisms, we show how the close proximity of high-power ASICs and temperature-sensitive photonic components fundamentally differentiates CPO from conventional electrical-only packaging. Thermal constraints related to lasers, PICs, EICs, FAU assembly, TIMs, and cooling solutions are reviewed within a unified framework, highlighting the strong interdependence between thermal behavior, optical performance, and packaging reliability. Looking forward, the scalability of CPO will depend on the co-optimization of thermal, electrical, and optical domains from the earliest stages of system design. Key priorities include improving wavelength stability in microring-based WDM systems, reducing thermal resistance in 3D-stacked architectures, and developing sustainable, high-efficiency cooling technologies. Although bandwidth density continues to drive CPO development, effective thermal management remains its indispensable foundation. This review consolidates current progress, identifies knowledge gaps, and provides guidance toward thermally robust, energy-efficient, and scalable CPO systems.

Acknowledgment. This work was supported by the Natural Science Foundation of Sichuan (Grant No. 2024NSFJQ0014) and the Chongqing Yingcai Project (Grant No. CQYC202201101417).

Zhonghua Yang received his BS degree in applied physics from Shenyang Aerospace University, Shenyang, China, in 2016 and his MS degree in optical engineering from University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2019. He was an assistant engineer with the Chongqing United Microelectronics Center (CUMEC), Chongqing, China, from 2019 to 2022. He is currently working toward his PhD with UESTC. His research interests include silicon photonics, optical communications, heterogeneous integration, co-packaged optics (CPO), chiplets, and advanced semiconductor packaging.

Guopeng He received his BS degree in mechanical engineering from Chang'an University, Xi’an, China, in 2024. He is currently pursuing his MS degree in integrated circuit engineering at University of Electronic Science and Technology of China, Chengdu, China. His research interests include mechanical manufacturing and thermal analysis of electronic chips.

Yufeng Li received his BS degree in applied physics from University of Science and Technology of China in 2004 and his PhD in applied physics from Rensselaer Polytechnic Institute in 2010. After graduation, he worked at the GE Global Research Center and Luminus Devices, focusing on the development of high-power LED technologies. He is currently with the University of Electronic Science and Technology of China. His research focuses on LED technologies, optical communications, co-packaged optoelectronics, and advanced packaging.

Yu Sun received his BS degree in material science and engineering from Tsinghua University, Beijing, China, in 2005 and his PhD in microelectronics and solid-state electronics from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China, in 2010. She was an associate researcher with the Institute of Microelectronics, Chinese Academy of Sciences, from 2010 to 2020. She is currently an associate researcher with the University of Electronic Science and Technology of China, Chengdu, China. Her research interests include optoelectronic technologies, co-packaged optics (CPO), system-in-package (SiP), chiplet, and advanced semiconductor packaging.

Wenbo Luo received his BSc degree in electronic science and technology and his PhD in material physics and chemistry from University of Electronic Science and Technology of China, Chengdu, China, in 2004 and 2010, respectively. He is currently working as a professor with the School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China. His current research interests include system-in-package (SiP), chiplet, and advanced semiconductor packaging.

Wanli Zhang received his PhD from University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2008. He is currently working as a professor with the School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China. He has published more than 40 publications in Journal of Magnetism and Magnetic Materials, IEEE Transactions on Magnetics, Materials Science Forum, Infrared Physics and Technology, and Chinese Physics Letters.